參數(shù)資料
型號(hào): EVAL-AD1937AZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 24/36頁(yè)
文件大小: 0K
描述: BOARD EVAL FOR AD1937
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
已用 IC / 零件: AD1937
主要屬性: 24 位,192 kHz,4 ADC: 107dB 動(dòng)態(tài)范圍,8 DAC: 112dB 動(dòng)態(tài)范圍
次要屬性: 分時(shí)復(fù)用(TDM)、I2C 和 SPI 接口,Popguard? 技術(shù)
已供物品:
AD1937
Rev. B | Page 30 of 36
Table 28. DACxx Volume Controls Registers (Address 6 to Address 13, 0x06 to 0x0D)
Bit
Value
Function
Description
7:0
0
No attenuation
DAC volume control
1 to 254
0.375 dB per step
255
Full attenuation
ADC CONTROL REGISTERS
Table 29. ADC Control 0 Register (Address 14, 0x0E)
Bit
Value
Function
Description
0
Normal
Power-down
1
Power down
1
0
Off
High-pass filter
1
On
2
0
Unmute
ADC1L mute
1
Mute
3
0
Unmute
ADC1R mute
1
Mute
4
0
Unmute
ADC2L mute
1
Mute
5
0
Unmute
ADC2R mute
1
Mute
7:6
00
32 kHz/44.1 kHz/48 kHz
Output sample rate
01
64 kHz/88.2 kHz/96 kHz
10
128 kHz/176.4 kHz/192 kHz
11
Reserved
Table 30. ADC Control 1 Register (Address 15, 0x0F)
Bit
Value
Function
Description
1:0
00
24 bits
Word width
01
20 bits
10
Reserved
11
16 bits
4:2
000
1 cycle (I2S mode)
ASDATA delay (BCLK periods)
001
0 (left-justified mode)
010
8 cycles (right-justified 24-bit mode)
011
12 cycles (right-justified 20-bit mode)
100
16 cycles (right-justified 16-bit mode)
101
Reserved
110
Reserved
111
Reserved
6:5
00
Stereo
Serial format
01
TDM single-line, standalone, and daisy-chain modes
10
TDM/AUX mode (ADC-, DAC-, TDM-coupled)
11
Reserved
7
0
Latch in midcycle (normal)
ABCLK active edge (TDM_IN)
1
Latch in at end of cycle (pipeline)
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