VDD = 2.3 V to" />
參數(shù)資料
型號: EVAL-AD5116EBZ
廠商: Analog Devices Inc
文件頁數(shù): 12/16頁
文件大小: 0K
描述: BOARD EVAL FOR AD5116
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
AD5116
Rev. B | Page 5 of 16
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Description
t
1
8
ms
Debounce time
t
2
1
sec
Manual to auto scan time
t
3
140
ms
Auto scan step
t
4
ASE = 0 V, PD = GND, PU = GND
1
sec
Auto save execute time
t
5
ASE = VDD
8
ms
Low pulse time to manual storage
t
EEPROM_PROGRAM
15
50
ms
Memory program time
t
POWER_UP
50
s
Power-on EEPROM restore time
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
2 Maximum time after V
DD is equal to 2.3 V.
TIMING DIAGRAMS
09657-
002
PU
RW
t1
PD (LOW)
Figure 2. Manual Increment Mode Timing
09657-
003
PU
t1
t2
t3
PD (LOW)
RW
Figure 3. Auto Increment Mode Timing
09657-
004
PD
t1
t4
EEPROM
DATA
NEW DATA
tEEPROM
PROGRAM
RW
ASE (LOW)
Figure 4. Auto Save Mode Timing
09657-
005
PD/PU (LOW)
t5
EEPROM
DATA
NEW DATA
tEEPROM
PROGRAM
ASE
Figure 5. Manual Save Mode Timing
09657-
006
PD
t1
RW
RW = 45
ASE
Figure 6. End Scale Indication Timing
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