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參數(shù)資料
型號： EVAL-AD5243SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/20頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5243
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD5243/AD5248
Rev. B | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 k VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
2
±0.1
+2
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
14
±2
+14
LSB
Nominal Resistor Tolerance3
RAB
TA = 25°C
20
+55
%
Resistance Temperature Coefficient
(RAB/RAB )/T
VAB = VDD, wiper = no connect
35
ppm/°C
Wiper Resistance
RWB
Code = 0x00, VDD = 5 V
160
200
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5
DNL
1.5
±0.1
+1.5
LSB
Integral Nonlinearity5
INL
2
±0.6
+2
LSB
Voltage Divider Temperature Coefficient
(VW/VW)/T
Code = 0x80
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0xFF
14
5.5
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
4.5
12
LSB
RESISTOR TERMINALS
Voltage Range6
VA, VB, VW
GND
VDD
V
Capacitance A, B7
CA, CB
f = 1 MHz, measured to GND,
code = 0x80
45
pF
Capacitance W7
CW
f = 1 MHz, measured to GND,
code = 0x80
60
pF
Shutdown Supply Current8
IA_SD
VDD = 5.5 V
0.01
1
A
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V
2.4
V
Input Logic Low
VIL
VDD = 5 V
0.8
V
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
A
Input Capacitance7
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3.5
6
A
Power Dissipation9
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
30
W
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%, code = midscale
±0.02
±0.08
%/%
DYNAMIC CHARACTERISTICS10
Bandwidth, 3 dB
BW
Code = 0x80
4.8
MHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.1
%
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB error band
1
s
Resistor Noise Voltage Density
eN_WB
RWB = 1.25 k, RS = 0
3.2
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
9
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use VDD = 5 V.
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