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參數(shù)資料
| 型號(hào)： | EVAL-AD5243SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5243 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
AD5243/AD5248
Data Sheet
Rev. B | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A, proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
VI
W
B
VO
04109-0-014
Figure 39. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
V
256
)
(
+
=
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, not on the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, as shown in Figure 40 and
Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital
input pins (AD5248 only).
LOGIC
340
GND
04109-0-015
Figure 40. ESD Protection of Digital Pins
A, B, W
GND
04109-0-016
Figure 41. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 VDD and GND power supply defines the
boundary conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on the A, B, and W terminals
that exceed VDD or GND are clamped by the internal forward-
biased diodes (see Figure 42).
GND
A
W
B
VDD
04109-0-017
Figure 42. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see Figure 42), it is important to
power VDD/GND before applying voltage to the A, B, and W
terminals; otherwise, the diode is forward-biased such that VDD
is powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, and VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important, as long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with disc or chip ceramic capacitors of 0.01 F
to 0.1 F. Low ESR 1 F to 10 F tantalum or electrolytic capacitors
should also be applied at the supplies to minimize any transient
disturbance and low frequency ripple (see Figure 43). In addition,
note that the digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
VDD
GND
VDD
C3
10
F
C1
0.1
F
AD5243
+
04109-0-018
Figure 43. Power Supply Bypassing
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