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參數(shù)資料
型號(hào)： EVAL-AD5273DBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5273DBZ
標(biāo)準(zhǔn)包裝： 1
系列： *
AD5273
Rev. H | Page 5 of 24
Parameter
Symbol
Test Conditions/Comments
Min
Max
Unit
Power Dissipation12
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
0.5
27.5
μW
Power Supply Sensitivity
PSRR
RAB = 1 kΩ
0.3
+0.3
%/%
PSRR
RAB = 10 kΩ, 50 kΩ, 100 kΩ
0.05
+0.05
%/%
DYNAMIC CHARACTERISTICS7, 13, 14
Bandwidth, 3 dB
BW_1 kΩ
RAB = 1 kΩ, code = 0x20
6000
kHz
BW_10 kΩ
RAB = 10 kΩ, code = 0x20
600
kHz
BW_50 kΩ
RAB = 50 kΩ, code = 0x20
110
kHz
BW_100 kΩ
RAB = 100 kΩ, code = 0x20
60
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, RAB = 1 kΩ, VB = 0 V,
f = 1 kHz
0.05
%
Adjustment Settling Time
tS1
VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW
5
μs
Power-Up Settling Time—
After Fuses Blown
tS2
VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW, VDD = 5 V
5
μs
Resistor Noise Voltage
eN_WB
RAB = 1 kΩ, f = 1 kHz, code = 0x20
3
nV/√Hz
INTERFACE TIMING CHARACTERISTICS7,14,15
Applies to all parts
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus Free Time Between
Stop and Start
t1
1.3
μs
tHD; STA Hold Time
(Repeated Start)
t2
After this period, the first clock
pulse is generated
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
50
μs
tSU; STA Setup Time for
Start Condition
t5
0.6
μs
tHD; DAT Data Hold Time
t6
0.9
μs
tSU; DAT Data Setup Time
t7
0.1
μs
tF Fall Time of Both SDA and
SCL Signals
t8
0.3
μs
tR Rise Time of Both SDA and
SCL Signals
t9
0.3
μs
tSU; STO Setup Time for Stop Condition
t10
0.6
μs
OTP Program Time
t11
400
ms
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 RWB/T = RWA/T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.
5 INL and DNL are measured at VW. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VW with the RDAC configured as a
potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating
conditions.
6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
7 Guaranteed by design; not subject to production test.
8 The minimum voltage requirement on the VIH is 0.7 × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
9 Different from the operating power supply; the power supply for OTP is used one time only.
10 Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.
11 See Figure 28 for the energy plot during the OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
14 All dynamic characteristics use VDD = 5 V.
15 See Figure 29 for the location of the measured values.
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