VDD 2 GND 3 SCL 4 A 8 B 7 " />
參數(shù)資料
型號(hào): EVAL-AD5273DBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 22/24頁(yè)
文件大小: 0K
描述: BOARD EVAL FOR AD5273DBZ
標(biāo)準(zhǔn)包裝: 1
系列: *
AD5273
Rev. H | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W
1
VDD 2
GND
3
SCL
4
A
8
B
7
AD0
6
SDA
5
AD5273
TOP VIEW
(Not to Scale)
03224-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
W
Wiper Terminal W. GND ≤ VW ≤ VDD.
2
VDD
Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, VDD_OTP
must be set within the window of 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options, or within the
window of 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH) options, and be capable of sourcing 100 mA.
3
GND
Common Ground.
4
SCL
Serial Clock Input. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up
resistor, ensure that the VIH minimum is 0.7 × VDD.
5
SDA
Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that the VIH minimum is 0.7 × VDD.
6
AD0
I2C Device Address Bit. Allows a maximum of two AD5273 devices to be addressed.
7
B
Resistor Terminal B. GND ≤ VB ≤ VDD.
8
A
Resistor Terminal A. GND ≤ VA ≤ VDD.
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