參數(shù)資料
型號: EVAL-AD5370EBZ
廠商: Analog Devices Inc
文件頁數(shù): 1/29頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD5370
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 40
位數(shù): 16
采樣率(每秒): 540k
數(shù)據(jù)接口: 串行
設(shè)置時間: 20µs
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD5370
40-Channel,16-Bit,
Serial Input, Voltage Output DAC
AD5370
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008 Analog Devices, Inc. All rights reserved.
FEATURES
40-channel DAC in a 64-lead LFCSP and a 64-lead LQFP
Guaranteed monotonic to 16 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage span of 4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
2.5 V to 5.5 V digital interface
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
AD5370
VREF0
SIGGND0
SIGGND4
SIGGND3
SIGGND2
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT16
TO
VOUT39
LDAC
DVCC
VDD
VSS AGND DGND
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
BUFFER
GROUP 0
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
STATE
MACHINE
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
DAC 7
OFFSET
DAC 0
BUFFER
OFS0
REGISTER
16
8
16
DAC 0
REGISTER
16
DAC 7
REGISTER
MU
X
2
MU
X
1
MU
X
1
MU
X
1
MU
X
1
TO
MUX2
A/B SELECT
REGISTER
CONTROL
REGISTER
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
16
X2A
REGISTER
X2B
REGISTER
16
MU
X
2
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
BUFFER
GROUP 1
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
OUTPUT BUFFER
AND
POWER-DOWN
CONTROL
DAC 7
OFFSET
DAC 1
DAC 0
BUFFER
OFS1
REGISTER
16
8
DAC 0
REGISTER
16
DAC 7
REGISTER
MU
X
2
TO
MUX2
A/B SELECT
REGISTER
X1A
REGISTER
X1B
REGISTER
C REGISTER
M REGISTER
16
MU
X
2
SIGGND1
GROUP 2 TO GROUP 4
ARE THE SAME AS GROUP 1
X2A
REGISTER
X2B
REGISTER
16
X2A
REGISTER
X2B
REGISTER
16
X2A
REGISTER
X2B
REGISTER
16
SERIAL
INTERFACE
05
81
3-
0
01
Figure 1.
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