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參數(shù)資料
| 型號(hào)： | EVAL-AD5370EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/29頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5370 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 40 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 540k |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 20µs |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5370 |
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AD5370
Rev. 0 | Page 3 of 28
GENERAL DESCRIPTION
The AD53701 contains forty 16-bit DACs in a single 64-lead
LFCSP and a 64-lead LQFP. The device provides buffered
voltage outputs with a span that is 4× the reference voltage. The
gain and offset of each DAC channel can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into five groups of eight DACs. Three offset DAC channels
allow the output range of blocks to be adjusted. Group 0 can be
adjusted by Offset DAC 0, Group 1 can be adjusted by Offset
DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.
The AD5370 offers guaranteed operation over a wide supply
range, with VSS from 16.5 V to 4.5 V and VDD from +9 V to
+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
The AD5370 has a high speed serial interface that is compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards
and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on receipt of new data. All the
outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect to
an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution
Nominal Output Span
Output Channels
Linearity Error (LSB)
16 bits
4 × VREF (20 V)
16
±4
14 bits
4 × VREF (20 V)
16
±1
16 bits
4 × VREF (20 V)
8
±4
14 bits
4 × VREF (20 V)
8
±1
AD5370
16 bits
4 × VREF (12 V)
40
±4
14 bits
4 × VREF (12 V)
40
±1
16 bits
4 × VREF (12 V)
32
±4
14 bits
4 × VREF (12 V)
32
±1
14 bits
±8.75 V
32
±3
14 bits
±8.75 V
40
±3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD5371EBZ | 功能描述:BOARD EVAL FOR AD5371 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5372EBZ | 功能描述:BOARD EVAL FOR AD5372 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5373EBZ | 功能描述:BOARD EVAL FOR AD5373 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5379EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC |
| EVAL-AD5379EBZ | 功能描述:BOARD EVALUATION FOR AD5379 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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