TA = 25°C, unle" />
參數(shù)資料
型號(hào): EVAL-AD5420EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 31/32頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD5420
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 1
位數(shù): 16
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 10µs
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD5420
AD5410/AD5420
Data Sheet
Rev. F | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
80 mA do not cause SCR latch-up.
Table 4.
Parameter
Rating
AVDD to GND
0.3 V to +60 V
DVCC to GND
0.3 V to +7 V
Digital Inputs to GND
0.3 V to DVCC + 0.3 V or +7 V
(whichever is less)
Digital Outputs to GND
0.3 V to DVCC + 0.3 V or +7 V
(whichever is less)
REFIN, REFOUT to GND
0.3 V to +7 V
IOUT to GND
0.3 V to AVDD
Operating Temperature Range
Industrial
40°C to +85°C1
Storage Temperature Range
65°C to +150°C
Junction Temperature (TJ max)
125°C
24-Lead TSSOP_EP Package
Thermal Impedance, θJA
35°C/W2
Thermal Impedance, θJC
9°C/W
40-Lead LFCSP Package
Thermal Impedance, θJA
33°C/W2
Thermal Impedance, θJC
4°C/W
Power Dissipation
(TJ max TA)/θJA
Lead Temperature
JEDEC industry standard
Soldering
J-STD-020
ESD (Human Body Model)
2 kV
1
Power dissipated on chip must be derated to keep junction temperature
below 125°C. The assumption is that the maximum power dissipation
condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip
current.
2
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. Ref: JEDEC JESD51 documents.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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