DV
參數(shù)資料
型號(hào)： EVAL-AD5420EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD5420
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 16
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 10µs
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD5420
Data Sheet
AD5410/AD5420
Rev. F | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
12
11
DVCC
FAULT
GND
LATCH
CLEAR
GND
SCLK
SDIN
GND
SDO
20
21
22
23
24
19
18
17
16
15
14
13
NC
CAP2
CAP1
R3SENSE
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
IOUT
BOOST
NC
DVCC SELECT
RSET
REFOUT
REFIN
AVDD
AD5410/
AD5420
TOP VIEW
(Not to Scale)
07
02
7-
0
05
Figure 5. TSSOP Pin Configuration
07
02
7-
05
3
PIN 1
INDICATOR
1
NC
2
3
GND
4
GND
5
CLEAR
6
LATCH
7
SCLK
8
SDIN
9
SDO
10
NC
23 DVCC SELECT
24 NC
25 R3SENSE
26 IOUT
27 BOOST
28 CAP1
29 CAP2
30 NC
22 NC
21 NC
1
N
C
1
2
G
N
D
1
3
G
N
D
1
5
G
N
D
1
7
R
E
F
O
U
T
1
6
R
S
E
T
1
8
R
E
F
IN
1
9
N
C
2
0
N
C
1
4
G
N
D
3
N
C
3
4
N
C
3
5
N
C
3
6
A
V
D
3
7
G
N
D
3
8
N
C
3
9
D
V
C
4
0
N
C
3
2
N
C
3
1
N
C
TOP VIEW
(Not to Scale)
AD5410/AD5420
FAULT
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
Figure 6. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP Pin No.
LFCSP Pin No.
Mnemonic
Description
1, 4, 5, 12
3, 4, 14, 15, 37
GND
These pins must be connected to ground.
2
39
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3
2
FAULT
Fault Alert. This pin is asserted low when an open circuit is detected between IOUT and
GND or an overtemperature is detected. The FAULT pin is an open-drain output and
must be connected to DVCC through a pull-up resistor (typically 10 kΩ).
6
5
CLEAR
Active High Input. Asserting this pin sets the output current to the zero-scale value,
which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA
to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.
7
6
LATCH
Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data
into the relevant register. In the case of the data register, the output current is also
updated.
8
7
SCLK
Serial Clock Input. Data is clocked into the input shift register on the rising edge of
SCLK. This operates at clock speeds of up to 30 MHz.
9
8
SDIN
Serial Data Input. Data must be valid on the rising edge of SCLK.
10
9
SDO
Serial Data Output. This pin is used to clock data from the device in daisy-chain or
readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and
11
12, 13
GND
Ground Reference Pin.
13
16
RSET
An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the overall performance of the device. See the Specifications and
14
17
REFOUT
Internal Reference Voltage Output. VREFOUT = 5 V ± 5 mV at TA = 25°C. Typical temperature
drift is 1.8 ppm/°C.
15
18
REFIN
External Reference Voltage Input. VREFIN = 5 V ± 50 mV for specified performance.
16
23
DVCC
SELECT
This pin, when connected to GND, disables the internal supply, and an external supply
must be connected to the DVCC pin. Leave this pin unconnected to enable the internal
supply. See the AD5410/AD5420 Features section.
17, 23
1, 10, 11, 19, 20,
21, 22, 24, 30,
31, 32, 33, 34,
35, 38, 40
NC
Do not connect to these pins.
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