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參數(shù)資料
| 型號(hào)： | EVAL-AD5425EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5425 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2.47M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 15ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5425 |
| 相關(guān)產(chǎn)品： | AD5425YRMZ-REEL7-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-REEL-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRM-REEL7-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-REEL-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-ND - IC DAC MULTIPLYING 8BIT 10-MSOP |
AD5425
Data Sheet
Rev. C | Page 18 of 24
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset vol-
tage. The input offset voltage of an op amp is multiplied by the
variable gain (due to the code dependent output resistance of
the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which if large enough, could cause the DAC to
be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent any significant errors.
Common-mode rejection of the op amp is important in voltage
switching circuits, since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at an 8-bit resolution.
Provided the DAC switches are driven from true wideband low
impedance sources (VIN and AGND), they settle quickly. Conse-
quently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is impor-
tant to minimize capacitance at the VREF node (voltage output
node in this application) of the DAC. This is done by using low
inputs capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. There is a large range of single-supply
amplifiers available from Analog Devices.
Table 7. Suitable ADI Precision References
Part No.
Output Voltage (V)
Initial Tolerance (%)
Temp Drift (ppm/°C)
I
SS (mA)
Output Noise (V p-p)
Package
ADR01
10
0.05
3
1
20
SOIC-8
ADR01
10
0.05
9
1
20
TSOT-23, SC70
ADR02
5
0.06
3
1
10
SOIC-8
ADR02
5
0.06
9
1
10
TSOT-23, SC70
ADR03
2.5
0.10
3
1
6
SOIC-8
ADR03
2.5
0.10
9
1
6
TSOT-23, SC70
ADR06
3
0.10
3
1
10
SOIC-8
ADR06
3
0.10
9
1
10
TSOT-23, SC70
ADR431
2.5
0.04
3
0.8
3.5
SOIC-8
ADR435
5
0.04
3
0.8
8
SOIC-8
ADR391
2.5
0.16
9
0.12
5
TSOT-23
ADR395
5
0.10
9
0.12
8
TSOT-23
Table 8. Suitable Precision ADI Op Amps
Part No.
Supply Voltage (V)
V
OS (Max) (V)
I
B (Max) (nA)
0.1 Hz to 10 Hz
Noise (V p-p)
Supply Current (A)
Package
OP97
±2 to ±20
25
0.1
0.5
600
SOIC-8
OP1177
±2.5 to ±15
60
2
0.4
500
MSOP, SOIC-8
AD8551
2.7 to 5
5
0.05
1
975
MSOP, SOIC-8
AD8603
1.8 to 6
50
0.001
2.3
50
TSOT
AD8628
2.7 to 6
5
0.1
0.5
850
TSOT, SOIC-8
Table 9. Suitable High Speed ADI Op Amps
Part No.
Supply Voltage (V)
BW @ ACL (MHz)
Slew Rate (V/s)
V
OS (Max) (V)
I
B (Max) (nA)
Package
AD8065
5 to 24
145
180
1500
6000
SOIC-8, SOT-23,MSOP
AD8021
±2.5 to ±12
490
120
1000
10500
SOIC-8, MSOP
AD8038
3 to 12
350
425
3000
750
SOIC-8, SC70-5
AD9631
±3 to ±6
320
1300
10000
7000
SOIC-8
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