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參數(shù)資料
| 型號： | EVAL-AD5425EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5425 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2.47M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 15ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5425 |
| 相關(guān)產(chǎn)品： | AD5425YRMZ-REEL7-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-REEL-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRM-REEL7-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-REEL-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-ND - IC DAC MULTIPLYING 8BIT 10-MSOP |
AD5425
Data Sheet
Rev. C | Page 20 of 24
ADSP-BF5xx-to-AD5425 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the ADSP-BF5xx
and the AD5425 DAC is shown in Figure 40. In this configura-
tion, data is transferred through the MOSI (master output/slave
input) pin. SYNC is driven by the SPI chip select pin, which is a
reconfigured programmable flag pin.
Figure 40. ADSP-BF5xx-to-AD5425 Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 41. When the SPORT is
enabled, initiate transmission by writing a word to the Tx
register. The data is clocked out on each rising edge of the DSP’s
serial clock and clocked into the DAC’s input shift register on
the falling edge of its SCLK. The DAC output is updated by
using the transmit frame synchronization (TFS) line to provide
a SYNC signal.
Figure 41. ADSP-BF5xx-to-AD5425 Interface
80C51/80L51-to-AD5425 Interface
A serial interface between the DAC and the 8051 is shown in
Figure 42. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, DIN. P3.3 is a bit-
programmable pin on the serial port that drives SYNC. When
data is transmitted to the switch, P3.3 is taken low. The 80C51/
80L51 transmits data in 8-bit bytes, which fits the AD5425 since
it only requires an 8-bit word. Data on RxD is clocked out of the
microcontroller on the rising edge of TxD and is valid on the
falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P3.3 is taken high at the
completion of this cycle. The 8051 provides the LSB of its SBUF
register as the first bit in the data stream. The DAC input reg-
ister requires that the MSB is the first bit received. The transmit
routine should take this into account.
Figure 42. 80C51/80L51-to-AD5425 Interface
MC68HC11 Interface-to-AD5425 Interface
Figure 43 shows an example of a serial interface between the
DAC and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and
the clock phase bit (CPHA) = 1. The SPI is configured by
writing to the SPI control register (SPCR) (see the MC68HC11
user manual). SCK of the MC68HC11 drives the SCLK of the
DAC interface, the MOSI output drives the serial data line, DIN,
of the AD5425. The SYNC signal is derived from a port line,
PC7. When data is being transmitted to the AD5425, the SYNC
line is taken low (PC7). Data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the
MC68HC11 is transmitted in 8-bit bytes with only 8 falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. PC7 is taken high at the end of the write.
Figure 43. 68HC11/68L11-to-AD5425 Interface
03161-040
SCLK
SCK
AD54251
SYNC
SPIxSEL
SDIN
MOSI
ADSP-BF5xx1
1 ADDITIONAL PINS OMITTED FOR CLARITY.
03161-041
SCLK
AD54251
SYNC
TFS
SDIN
DT
ADSP-BF5xx1
1 ADDITIONAL PINS OMITTED FOR CLARITY.
03161-042
SYNC
P1.1
AD54251
SCLK
TxD
SDIN
RxD
80511
1 ADDITIONAL PINS OMITTED FOR CLARITY.
03161-043
MOSI
AD54251
SCLK
PC7
SDIN
SCK
MC68HC111
1 ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
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