8-/10-/12-Bit High Bandwidth
Multiplying DACs with Serial Interface
Data Sheet
AD5426/AD5432/AD5443
Rev. G
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FEATURES
2.5 V to 5.5 V supply operation
50 MHz serial interface
10 MHz multiplying bandwidth
2.5 MSPS update rate
INL of ±1 LSB for 12-bit DAC
±10 V reference input
Low glitch energy < 2 nV-s
Extended temperature range 40°C to +125°C
10-lead MSOP package
Pin-compatible 8-, 10-, and 12-bit current output DACs
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
Daisy-chain mode
Readback function
0.4 A typical power consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
current output digital-to-analog converters (DACs), respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suitable for battery-powered applications and
many other applications.
These DACs use a double buffered, 3-wire serial interface that is
compatible with SPI, QSPI, MICROWIRE, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift register
and latches are filled with 0s and the DAC outputs are at zero scale.
As a result of manufacturing on a CMOS submicron process,
the parts offer excellent 4-quadrant multiplication characteristics
with large signal multiplying bandwidths of 10 MHz. The applied
external reference input voltage, VREF, determines the full-scale
output current. An integrated feedback resistor, RFB, provides
temperature tracking and full-scale voltage output when combined
with an external current to voltage precision amplifier.
10-lead MSOP packages.
The EV-AD5443/46/53SDZ evaluation board is available for
evaluating DAC performance. For more information, see the
FUNCTIONAL BLOCK DIAGRAM
SCLK
SYNC
AD5426/
AD5432/
AD5443
VREF
IOUT2
IOUT1
RFB
R
8-/10-/12-BIT
R-2R DAC
DAC REGISTER
SDIN
VDD
GND
POWER-ON
RESET
CONTROL LOGIC AND
INPUT SHIFT REGISTER
INPUT LATCH
SDO
03162-001
Figure 1.
1
U.S. Patent No. 5,689,257.