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參數(shù)資料
| 型號： | EVAL-AD5546SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5546 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
Data Sheet
AD5546/AD5556
Rev. D | Page 7 of 20
Pin No.
Mnemonic
Description
13
REF
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14
IOUT
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
15
LDAC
Digital Input Load DAC Control. The signal level must be ≤ VDD + 0.3 V.
16
WR
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17
MSB
Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
18
RS
Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
19
GND
Analog and Digital Grounds.
20 to 27
D13 to D6
Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V.
28
VDD
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
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