參數(shù)資料
型號: EVAL-AD5546SDZ
廠商: Analog Devices Inc
文件頁數(shù): 2/20頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5546
標準包裝: 1
系列: *
AD5546/AD5556
Data Sheet
Rev. D | Page 10 of 20
CIRCUIT OPERATION
DIGITAL-TO-ANALOG (DAC) CONVERTER SECTION
The AD5546/AD5556 are 16-/14-bit multiplying, current out-
put, and parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply and provide both unipolar 0 V to –VREF, or
0 V to +VREF, and bipolar ±VREF output ranges from a –18 V to
+18 V reference. In addition to the precision conversion RFB
commonly found in current output DACs, there are three addi-
tional precision resistors for four-quadrant bipolar applications.
The AD5546/AD5556 consist of two groups of precision R-2R
ladders, which make up the 12/10 LSBs, respectively. Further-
more, the four MSBs are decoded into 15 segments of resistor
value 2R. Figure 17 shows the architecture of the 16-bit AD5546.
Each of the 16 segments in the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor, RFB, and four-quadrant resistor, ROFS, have values of 10
kΩ. Each four-quadrant resistor, R1 and R2, equals 5 kΩ. In
four-quadrant operation, R1, R2, and an external op amp work
together to invert the reference voltage and apply it to the REF
input. With ROFS and RFB connected as shown in Figure 2, the
output can swing from –VREF to +VREF.
The reference voltage inputs exhibit a constant input resistance
of 5 kΩ ±20%. The DAC output, IOUT, impedance is code depen-
dent. External amplifier choice should take into account the
variation of the AD5546/AD5556 output impedance. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended to bypass the power supply
with a 0.01 μF to 0.1 μF ceramic or chip capacitor in parallel
with a 1 μF tantalum capacitor. Also, to minimize gain error,
PCB metal traces between VREF and RFB should match.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 20 pF capacitor is
generally adequate for the compensation.
The VDD power is used primarily by the internal logic and to
drive the DAC switches. Note that the output precision
degrades if the operating voltage falls below the specified
voltage. The user should also avoid using switching regulators
because device power supply rejection degrades at higher
frequencies.
03
81
0-
0
19
2R
80k
R
40k
2R
80k
2R
80k
2R
80k
2R
80k
2R
80k
R
40k
2R
80k
R
2R
80k
R
2R
80k
R
2R
80k
R
2R
80k
2R
80k
R
40k
R2
5k
R1
5k
REF
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
RCOM
R1
ADDRESS DECODER
DAC REGISTER
INPUT REGISTER
LDAC
WR
RS
4 MSB
15 SEGMENTS
8-BIT R–2R
4-BIT R–2R
16
8
4
LDAC
WR
D15 D14
D0
RS
10k
ROFS
RFB
IOUT
GND
RA
RB
Figure 17. 16-Bit AD5546 Equivalent R-2R DAC Circuit with Digital Section
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