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參數(shù)資料
| 型號： | EVAL-AD7192EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7192 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 輸入范圍： | ±VREF/增益 |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7192 |
| 已供物品： | 板 |
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AD7192
Rev. A | Page 7 of 40
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments1, 2
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
READ OPERATION
t1
0
ns min
CS falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after CS inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to CS inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
WRITE OPERATION
t8
0
ns min
CS falling edge to SCLK active edge setup time4
t9
30
ns min
Data valid to SCLK edge setup time
t10
25
ns min
Data valid to SCLK edge hold time
t11
0
ns min
CS rising edge to SCLK edge hold time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
CIRCUIT AND TIMING DIAGRAMS
ISINK (1.6mA WITH DVDD = 5V,
100A WITH DVDD = 3V)
ISOURCE (200A WITH DVDD = 5V,
100A WITH DVDD = 3V)
1.6V
TO
OUTPUT
PIN
50pF
0
78
22
-0
02
Figure 2. Load Circuit for Timing Characterization
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7192EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD7192 24BIT ADC |
| EVAL-AD7193EBZ | 功能描述:EVAL BOARD FOR AD7193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7194EBZ | 功能描述:EVAL BOARD FOR AD7194 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7195EBZ | 功能描述:BOARD EVAL FOR AD7195 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD7262EDZ | 功能描述:BOARD EVAL CONTROL AD7262 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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