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| 型號： | EVAL-AD7193EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7193 |
| 設(shè)計資源： | EVAL-AD7193 Schematic AD7193 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7193 |
| 已供物品： | 板，線纜 |
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Data Sheet
AD7193
Rev. D | Page 11 of 56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLK2
SCLK
CS
P1/REFIN2(+)
P2
P3
MCLK1
DOUT/RDY
SYNC
DVDD
AGND
DGND
AVDD
P0/REFIN2(–)
NC
AINCOM
AIN4
AIN2
AIN1
BPDSW
REFIN1(–)
REFIN1(+)
AIN5
AIN3
AIN6
AIN7
AIN8
DIN
AD7193
TOP VIEW
(Not to Scale)
08367-
005
Figure 5. 28-lead TSSOP Pin Configuration
Table 5. 28-lead TSSOP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
MCLK1
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
2
MCLK2
Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
3
SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
4
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
5
P3
Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and
AGND.
6
P2
Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and
AGND.
7
P1/REFIN2(+)
Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced
between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as
REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(). REFIN2(+) can lie
anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) REFIN2()), is AVDD, but
the part functions with a reference from 1 V to AVDD.
8
P0/REFIN2()
Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced
between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as
REFIN2(). This reference input can lie anywhere between AGND and AVDD 1 V.
9
NC
No Connect. Tie this pin to AGND.
10
AINCOM
Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential
operation.
11
AIN1
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN2 or as a pseudo differential input when used with AINCOM.
12
AIN2
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN1 or as a pseudo differential input when used with AINCOM.
13
AIN3
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudo differential input when used with AINCOM.
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