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參數(shù)資料
| 型號： | EVAL-AD7193EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7193 |
| 設(shè)計資源： | EVAL-AD7193 Schematic AD7193 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7193 |
| 已供物品： | 板，線纜 |
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AD7193
Data Sheet
Rev. D | Page 14 of 56
Pin No.
Mnemonic
Description
21
AGND
Analog Ground Reference Point.
22
DGND
Digital Ground Reference Point.
23
AVDD
Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with
AVDD at 5 V or vice versa.
24
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
25
SYNC
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration
control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital
interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD.
27
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
28
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
29
MCLK1
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
30
MCLK2
Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a
crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin
can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
31
SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information transmitted to or from the ADC in smaller batches of data.
32
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
EPAD
The exposed pad must be connected to AGND.
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