- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17048 > EVAL-AD7194EBZ (Analog Devices Inc)EVAL BOARD FOR AD7194 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-AD7194EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 37/57頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR AD7194 |
| 設(shè)計(jì)資源： | EVAL-AD7zzzEBZ Schematic AD7194 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7194 |
| 已供物品： | 板，線纜 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)
Data Sheet
AD7194
Rev. A | Page 41 of 56
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 34 shows the
frequency response of the sinc4 filter. The filter provides 50 Hz
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable 4.92 MHz master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
FI
L
T
E
R
G
AI
N
(
d
B)
08566-
033
Figure 34. Sinc4 Filter Response (FS[9:0] = 96, REJ60 = 1)
SINC3 FILTER (CHOP DISABLED)
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the SINC3 bit in the mode register. The sinc3
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
08566-
034
Figure 35. Sinc3 Filter (Chop Disabled)
Sinc3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
tSETTLE = 3/fADC
The 3 dB frequency is equal to
f3dB = 0.272 × fADC
Table 30 gives some examples of FS settings and the corres-
ponding output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
10
300
96
50
60
80
60
50
When a channel change occurs, the modulator and filter reset.
The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 36). Subsequent
conversions on this channel are available at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
08566-
035
Figure 36. Sinc3 Channel Change
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the
programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes four conversions after
the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08566-
036
Figure 37. Asynchronous Step Change in Analog Input
Sinc3 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ECC22DCMT-S288 | CONN EDGECARD 44POS .100 EXTEND |
| 0210490257 | CABLE JUMPER 1.25MM .051M 20POS |
| ADR445ARMZ-REEL7 | IC VREF SERIES PREC 5V 8-MSOP |
| RBC19DRYN-S13 | CONN EDGECARD 38POS .100 EXTEND |
| HKQ0603S0N7C-T | INDUCTOR HI FREQ 0.7NH 0201 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7195EBZ | 功能描述:BOARD EVAL FOR AD7195 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD7262EDZ | 功能描述:BOARD EVAL CONTROL AD7262 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7264EDZ | 功能描述:BOARD EVALUATION FOR AD7264 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7265CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
| EVAL-AD7265CB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。