AVDD Analog " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EVAL-AD7194EBZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 4/57闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� EVAL BOARD FOR AD7194
瑷�(sh猫)瑷�(j矛)璩囨簮锛� EVAL-AD7zzzEBZ Schematic
AD7194 Gerber Files
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
ADC 鐨勬暩(sh霉)閲忥細 1
浣嶆暩(sh霉)锛� 24
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
宸ヤ綔婧害锛� -40°C ~ 105°C
宸茬敤 IC / 闆朵欢锛� AD7194
宸蹭緵鐗╁搧锛� 鏉�锛岀窔绾�
Data Sheet
AD7194
Rev. A | Page 11 of 56
Pin No.
Mnemonic
Description
23
AVDD
Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V
with AVDD at 5 V or vice versa.
24
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
25
SYNC
Logic input that allows for synchronization of the digital filters and analog modulators when using a
number of AD7194 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor
internally to DVDD.
26
NC
No Connect. Do not connect to this pin.
27
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data from
any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low
to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high
before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,
indicating that valid data is available. With an external serial clock, the data can be read using the
DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the
SCLK falling edge and is valid on the SCLK rising edge.
28
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
29
MCLK1
When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
30
MCLK2
Master Clock Signal for the Device. The AD7194 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7194 can also be provided externally in the form of
a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2
pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
31
SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a nonconti-
nuous clock with the information transmitted to or from the ADC in smaller batches of data.
32
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the
ADC in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode
with SCLK, DIN, and DOUT used to interface with the device.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ECC22DCMT-S288 CONN EDGECARD 44POS .100 EXTEND
0210490257 CABLE JUMPER 1.25MM .051M 20POS
ADR445ARMZ-REEL7 IC VREF SERIES PREC 5V 8-MSOP
RBC19DRYN-S13 CONN EDGECARD 38POS .100 EXTEND
HKQ0603S0N7C-T INDUCTOR HI FREQ 0.7NH 0201
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
EVAL-AD7195EBZ 鍔熻兘鎻忚堪:BOARD EVAL FOR AD7195 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版紨绀烘澘鍜屽浠� 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 涓昏鐩殑:闆讳俊锛岀窔璺帴鍙e柈鍏冿紙LIU锛� 宓屽叆寮�:- 宸茬敤 IC / 闆朵欢:IDT82V2081 涓昏灞€�:T1/J1/E1 LIU 娆¤灞€�:- 宸蹭緵鐗╁搧:鏉匡紝闆绘簮锛岀窔绾滐紝CD 鍏跺畠鍚嶇ū:82EBV2081
EVAL-AD7262EDZ 鍔熻兘鎻忚堪:BOARD EVAL CONTROL AD7262 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- ADC 鐨勬暩(sh霉)閲�:1 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:94.4k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:USB 杓稿叆鑼冨湇:±VREF/2 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛�:- 宸ヤ綔婧害:-40°C ~ 85°C 宸茬敤 IC / 闆朵欢:MAX11645 宸蹭緵鐗╁搧:鏉匡紝杌熶欢
EVAL-AD7264EDZ 鍔熻兘鎻忚堪:BOARD EVALUATION FOR AD7264 RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- ADC 鐨勬暩(sh霉)閲�:1 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:94.4k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:USB 杓稿叆鑼冨湇:±VREF/2 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛�:- 宸ヤ綔婧害:-40°C ~ 85°C 宸茬敤 IC / 闆朵欢:MAX11645 宸蹭緵鐗╁搧:鏉�锛岃粺浠�
EVAL-AD7265CB 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
EVAL-AD7265CB1 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC