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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EVAL-AD7366CBZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | BOARD EVALUATION FOR AD7366 |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | iCMOS® |
| ADC 鐨勬暩(sh霉)閲忥細 | 2 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杓稿叆鑼冨湇锛� | ±10 V |
| 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯欐簴锛夛細 | 70mW @ 1MSPS |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 宸茬敤 IC / 闆朵欢锛� | AD7366 |
| 宸蹭緵鐗╁搧锛� | 鏉� |
| 鐩搁棞鐢�(ch菐n)鍝侊細 | AD7366BRUZ-5-ND - IC ADC 12BIT DUAL 500KSPS 24-TSS AD7366BRUZ-5500RL7-ND - IC ADC 12BIT DUAL BIPO 24-TSSOP AD7366BRUZ-5-RL7-ND - IC ADC 12BIT DUAL BIPO 24-TSSOP AD7366BRUZ-ND - IC ADC 12BIT SAR 1MSPS 24TSSOP AD7366BRUZ-RL7-ND - IC ADC 12BIT SAR 1MSPS 24TSSOP AD7366BRUZ-500RL7-ND - IC ADC 12BIT SAR 1MSPS 24TSSOP |
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AD7366/AD7367
Rev. D | Page 3 of 28
SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = 16.5 V to 11.5 V, VDRIVE = 2.7 V to 5.25 V, fS = 1.12 MSPS, fSCLK = 48 MHz,
VREF = 2.5 V internal/external, TA = 40掳C to +85掳C, unless otherwise noted.
Table 2. AD7366
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
f
IN = 50 kHz sine wave
Signal-to-Noise Ratio (SNR)1
70
72
dB
Signal-to-Noise + Distortion Ratio (SINAD)1
70
71
dB
Total Harmonic Distortion (THD)1
85
78
dB
Spurious-Free Dynamic Range (SFDR)
87
78
dB
Intermodulation Distortion (IMD)1
fa = 49 kHz, fb = 51 kHz
Second-Order Terms
88
dB
Third-Order Terms
88
dB
Channel-to-Channel Isolation1
90
dB
SAMPLE AND HOLD
Aperture Delay2
10
ns
Aperture Jitter2
40
ps
Aperture Delay Matching2
卤100
ps
Full Power Bandwidth
35
MHz
@ 3 dB, 卤10 V range
8
MHz
@ 0.1 dB, 卤10 V range
DC ACCURACY
Resolution
12
Bits
Integral Nonlinearity (INL)1
卤0.5
卤1
LSB
Differential Nonlinearity (DNL)1
卤0.25
卤0.5
LSB
Guaranteed no missed codes to 12 bits
Positive Full-Scale Error1
卤1
卤7
LSB
卤5 V and 卤10 V analog input range
卤1
卤6
LSB
0 V to 10 V analog input range
Positive Full-Scale Error Match1
卤1.5
LSB
Matching from ADC A to ADC B
卤0.1
LSB
Channel-to-channel matching for ADC A and
ADC B
Zero Code Error1
卤0.5
卤3
LSB
卤5 V and 卤10 V analog input range
卤1
卤6
LSB
0 V to 10 V analog input range
Zero Code Error Match1
卤1.5
LSB
Matching from ADC A to ADC B
卤0.1
LSB
Channel-to-channel matching for ADC A and
ADC B
Negative Full-Scale Error1
卤1
卤7
LSB
卤5 V and 卤10 V analog input range
卤1
卤6
LSB
0 V to 10 V analog input range
Negative Full-Scale Error Match1
卤1.5
LSB
Matching from ADC A to ADC B
卤0.1
LSB
Channel-to-channel matching for ADC A and
ADC B
ANALOG INPUT
Input Voltage Ranges
Programmed via RANGE pins; see Table 8
卤10
V
卤5
V
0 to 10
V
DC Leakage Current
卤0.01
卤1
A
Input Capacitance
9
pF
When in track, 卤10 V range
13
pF
When in track, 卤5 V and 0 V to 10 V range
Input Impedance
260
k惟
卤10 V @ 1 MSPS
2.5
M惟
卤10 V @ 100 kSPS
125
k惟
卤5 V and 0 V to 10 V range @ 1 MSPS
1.2
M惟
卤5 V and 0 V to 10 V range @ 100 kSPS
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