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參數(shù)資料
| 型號： | EVAL-AD7699EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7699 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | 0 ~ Vdd |
| 在以下條件下的電源（標準）： | 28mW @ 500kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7699 |
| 已供物品： | 板 |
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Data Sheet
AD7699
Rev.
| Page 25 of 28
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
This mode is used when the AD7699 is connected to any host
using an SPI, serial port, or FPGA with an interrupt input. The
connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40. For SPI, the host
should use CPHA = CPOL = 1. Reading/writing spanning
conversion is shown, which covers all three modes detailed in
the Digital Interface section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned low before the
safe data transfer time, tDATA, and then held low beyond the
conversion time, tCONV, to generate the busy signal indicator.
When the conversion is complete, SDO transitions from high
impedance to low with a pull-up to VIO, which can be used to
interrupt the host to begin data transfer.
After the conversion is complete, the AD7699 enters the
acquisition phase and power-down. The host must enable the
MSB of CFG at this time (if necessary) to begin the CFG
update. While CNV is low, both a CFG update and a data
readback take place. The first 14 SCK rising edges are used to
update the CFG register, and the first 16 SCK falling edges clock
out the conversion results starting with the MSB. The restriction
for both configuring and reading is that they both occur before
the tDATA time elapses for the next conversion. All 14 bits of
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before tDATA elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
SDO returns to high impedance. Note that, if the optional SCK
falling edge is not used, the busy feature cannot be detected if
the LSB for the conversion is low.
If CFG readback is enabled, the CFG register associated with
the conversion result (n 1) is read back MSB first following
the LSB of the conversion result. A total of 31 SCK falling edges
is required to return SDO to high impedance if this is enabled.
AD7699
MISO
MOSI
SCK
SS
SDO
VIO
FOR SPI USE CPHA = 1, CPOL = 1.
SCK
CNV
DIN
DIGITAL HOST
IRQ
0
73
54
-03
7
Figure 39. Connection Diagram for the AD7699 with a Busy Indicator
SCK
ACQUISITION (n)
ACQUISITION
(n + 1)
CNV
DIN
SDO
MSB
– 1
1
2
BEGIN DATA (n – 1)
BEIGN CFG (n + 1)
CFG
MSB
LSB
+ 1
LSB
15
SEE NOTE
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
16
17/
31
17/
31
CONVERSION (n)
CONVERSION
(n – 1)
(QUIET
TIME)
END DATA (n – 2)
END DATA (n – 1)
END CFG (n + 1)
END CFG (n)
X
XX
X
tDATA
UPDATE (n + 1)
CFG/SDO
LSB
+ 1
LSB
CONVERSION (n – 1)
(QUIET
TIME)
UPDATE (n)
CFG/SDO
tCYC
tACQ
tHDIN
tHSDO
tDSDO
tSDIN
tDATA
tCONV
tCNVH
tDIS
tEN
CFG
MSB –1
07
35
4-
03
8
tSCK
tSCKH
tSCKL
Figure 40. Serial Interface Timing for the AD7699 with a Busy Indicator
B
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