- 您現在的位置：買賣IC網 > PDF目錄17052 > EVAL-AD7725CBZ (Analog Devices Inc)BOARD EVALUATION FOR AD7725 PDF資料下載
參數資料
| 型號： | EVAL-AD7725CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7725 |
| 標準包裝： | 1 |
| ADC 的數量： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 900k |
| 數據接口： | 串行，并聯(lián) |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 615mW @ 900kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7725 |
| 已供物品： | 板，CD |
| 相關產品： | AD7725BSZ-ND - IC ADC 16BIT PROG 44MQFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. A
–22–
AD7725
Status Register
The status register is a 16-bit register that provides the user with
information about the status of the device. The information avail-
able to the user includes whether a configuration file was loaded
successfully, what errors if any, occurred the last instruction
written, and other information that may be useful to the user
when operating the device. To read the status register, RS is
taken high and RD/
WR is taken high. When CS is taken low, the
contents of the status register will be output. The status register is
shown in Table II and the instruction set in Table III.
Table II. Status Register
Bit
Name
Function
15
InstrBUSY
This bit is set to 1 when an
instruction is performed.
14
Data Ready
This bit is set to 1 when data is
ready to be read from the device
(a read data cycle is required).
13
Data Request
This bit is set to 1 when the device.
requires data to be written to it (a write
data cycle is required).
12
ID Error
This bit is set to 1 if the programming
data has an incorrect ID value.
11
CRC Error
This bit is set to 1 if corrupt
data is loaded into the device.
10
Data Error
This bit is set to 1 if an overflow occurs
to indicate that the conversion result is
invalid.
9
InstrReg[15]
Instruction Register Bit 15
8
InstrReg[13]
Instruction Register Bit 13
7
InstrReg[12]
Instruction Register Bit 12
6
InstrReg[11]
Instruction Register Bit 11
5
InstrReg[6]
Instruction Register Bit 6
4
InstrReg[5]
Instruction Register Bit 5
3
InstrReg[4]
Instruction Register Bit 4
2
InstrReg[1]
Instruction Register Bit 1
1
InstrReg[0]
Instruction Register Bit 0
0
CFGEND
Configuration End Flag. This is set to 1
when the device has been configured
correctly and is ready to start converting.
Table III. Instruction Set for Parallel Mode
Instruction
Hex Code
Description
RdID
0x8802
Read Device ID
RdCONV
0x8D21
Read Converter Data. When
this instruction is issued to the
AD7725, the device continues to
output conversion data until the
ABORT instruction is issued.
WrConfig
0x1800
Write Configuration Data
WrConfigEM
0x1A00
Write Configuration Data,
Mask Errors
ABORT
0x0000
Abort. This instruction is a
soft reset, that is, it breaks the
conversion process and leaves
the device in a clean state,
still configured, ready for the
next instruction.
BFR
0x2000
Boot from Internal ROM
Configuring the Device
Following power-up, the AD7725 is configured by loading a user-
defined filter from an external source via the parallel interface.
Three instructions are provided for configuring the AD7725 (see
Table III).
WrConfig (Write Configuration)
When this instruction is issued, the device generates an
interrupt every time a new word of the configuration data is
required. The interrupt is cleared on the falling edge of
CS
during the data write cycle. This continues until the com-
plete file is written. Immediately after the last word of the
configuration data is written, a final interrupt is asserted to
indicate “Instruction Done.”
However, if an error occurred during the configuration
process, for example, if the configuration data is corrupt or
in the wrong format, an interrupt will be asserted.
It is advised that when using this instruction, the status regis-
ter be read after each interrupt to ensure no errors occurred
and that the correct response is made. If configuration data is
corrupt, it will not be internally written to the postprocessor.
WrConfigEM (Write Configuration with Error Mask)
When this instruction is issued, no interrupts to signal errors
will ever be asserted during the download of the configura-
tion file. This saves reading the status register in response
to every interrupt as with the previous instruction. The
configuration process will always run through the 504
(42 writes
12 blocks) data write cycles in the configura-
tion file and once this is complete, the “Instruction Done”
interrupt is issued. In this case, the status register should be
checked at the end of the configuration to verify whether
any errors occurred. If configuration data is corrupt, it will
not be internally written to the postprocessor.
For evaluation purposes, the user can load the default filter
stored in internal ROM into the postprocessor. In this case the
following instruction should be issued:
BFR (Boot from ROM)
This instruction informs the device to load the configuration
data for the default filter stored in internal ROM.
相關PDF資料 |
PDF描述 |
|---|---|
| REC5-4805SRW/H6/C | CONV DC/DC 5W 36-72VIN 05VOUT |
| REC5-4805SRW/H6/A | CONV DC/DC 5W 36-72VIN 05VOUT |
| EVAL-AD7796EBZ | BOARD EVALUATION FOR AD7796 |
| GSM10DRSI-S288 | CONN EDGECARD 20POS .156 EXTEND |
| ECC50DJBN | CONN EDGECARD 100POS .100X.200 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EVAL-AD7730EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7730EBZ | 功能描述:BOARD EVAL FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7730LEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7730LEBZ | 功能描述:BOARD EVALUATION FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7731EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。