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參數(shù)資料
| 型號(hào)： | EVAL-AD7734EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 17/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7734 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.4k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 85mW @ 5V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7734 |
| 已供物品： | 板，纜線，CD |
| 產(chǎn)品目錄頁(yè)面： | 779 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7734BRUZ-REEL7TR-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-REEL-ND - IC ADC 24BIT 4CH SIG-DEL 28TSSOP AD7734BRUZ-ND - IC ADC 24BIT 4-CH 28-TSSOP AD7734BRU-ND - IC ADC 24BIT 4-CH 28-TSSOP |
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AD7734
Data Sheet
Rev. A | Page 24 of 32
DUMP MODE
When the DUMP bit in the mode register is set to 1, the
channel status register will be read immediately by a read of the
channel data register, regardless of whether the status or the
data register has been addressed through the communications
register. The DIN pin should not be high while reading 24-bit
data in dump mode; otherwise, the AD7734 will be reset.
Figure 18 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 status register and data register in
the dump mode.
CONTINUOUS CONVERSION MODE
When the mode register is being written, the ADC status byte is
cleared and the RDY pin goes high, regardless of its previous
state. When the continuous conversion command is written to
the mode register, the ADC starts conversion on the channel
selected by the address of the mode register.
After the conversion is complete, the relevant channel data
register and channel status register are updated, the relevant
RDY bit in the ADC status register is set, and the AD7734
continues converting on the next enabled channel. The part will
cycle through all enabled channels until put into another mode
or reset. The cycle period will be the sum of all enabled
channels’ conversion times, set by the corresponding channel
conversion time registers.
The RDY bit is reset when the relevant channel data register is
being read. The behavior of the RDY pin depends on the
RDYFN bit in the I/O port register. When the RDYFN bit is 0,
the RDY pin goes low when any channel has unread data. When
the RDYFN bit is set to 1, the RDY pin will only go low if all
enabled channels have unread data.
If an ADC conversion result has not been read before a new
ADC conversion is completed, the new result will overwrite the
previous one. The relevant RDY bit goes low and the RDY pin
goes high for at least 163 MCLK cycles (~26.5 s), indicating
when the data register is updated, and the previous conversion
data is lost.
If the data register is being read as an ADC conversion
completes, the data register will not be updated with the new
result (to avoid data corruption) and the new conversion
data is lost.
Figure 19 shows the digital interface signal’s sequence for the
continuous conversion mode with Channels 0 and 1 enabled
and the RDYFN bit set to 0. The RDY pin goes low and the data
register is read after each conversion. Figure 20 shows a similar
sequence but with the RDYFN bit set to 1. The RDY pin goes
low and all data registers are read after all conversions are
completed. Figure 21 shows the RDY pin when no data are read
from the AD7734.
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA
REGISTER
READ
CHANNEL
STATUS
38h
48h
WRITE
COMMUNICATIONS
REGISTER
(00h)
STATUS
DATA
Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bits Data Reading, Dump Mode
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
READ
DATA
CH1
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
CH1 CONVERSION
READ
DATA
CH0
CH0 CONVERSION
READ
DATA
CH1
Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0
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