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參數(shù)資料
| 型號： | EVAL-AD7762EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL CONTROL AD7762 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±3.25 Vpp |
| 在以下條件下的電源（標準）： | 958mW @ 625kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7762 |
| 已供物品： | 板，CD |
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Data Sheet
AD7762
Rev. A | Page 23 of 28
AD7762 REGISTERS
The AD7762 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter
configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers
involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are
given here.
CONTROL REGISTER 1—REG 0X0001
Default Value 0x001A
MSB
LSB
DL_Filt
RD Ovr
RD Gain
RD Off
RD Stat
0
SYNC
FLEN3
FLEN2
FLEN1
FLEN0
BYP F3
1
DEC2
DEC1
DEC0
Table 15.
Bit
Mnemonic
Description
15
DL_Filt1
Download Filter. Before downloading a user-defined filter, this bit must be set. The Filter Length bits must also be set at
this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the
coefficients and the checksum have been written.
14
RD Ovr1, 2
Read Overrange. If this bit has been set, the next read operation outputs the contents of the Overrange Threshold
Register instead of a conversion result.
13
RD Gain1, 2
Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register.
12
RD Off1, 2
Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register.
11
RD Stat1, 2
Read Status. If this bit has been set, the next read operation outputs the contents of the status register.
10
0
0 must be written to this bit.
9
SYNC1
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
8-5
FLEN3:0
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
4
BYP F3
Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed.
3
1
1 must be written to this bit.
2-0
DEC2:0
Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1
corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on up to the maximum value of 5,
corresponding to 32× decimation.
1
Bit 15 to Bit 9 are all self clearing bits.
2
Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation.
CONTROL REGISTER 2—ADDRESS 0X0002
Default Value 0x009B
MSB
LSB
0
CDIV
0
PD
LPWR
1
D1PD
Table 16.
Bit
Mnemonic
Description
5
CDIV
Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the
MCLK by 2. If CDIV = 1, then the ICLK frequency is equal to the MCLK.
3
PD
Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW.
2
LPWR
Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for a 6 dB
reduction in noise performance.
1
Write 1 to this bit.
0
D1PD
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
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