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| 型號： | EVAL-AD7762EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL CONTROL AD7762 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±3.25 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 958mW @ 625kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7762 |
| 已供物品： | 板，CD |
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Data Sheet
AD7762
Rev. A | Page 13 of 28
THEORY OF OPERATION
The AD7762 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
Due to the high oversampling rate, that spreads the
quantization noise from 0 to fICLK, the noise energy contained in
the band of interest is reduced (Figure 22 a). To further reduce
the quantization noise, a high order modulator is employed to
shape the noise spectrum; so that most of the noise energy is
shifted out of the band of interest (Figure 22 b).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (Figure 22 c) while also
reducing the data rate from fICLK at the input of the filter to
fICLK/8 or less at the output of the filter, depending on the
decimation rate used.
Digital filtering has certain advantages over analog filtering. It
does not introduce significant noise or distortion and can be
made perfectly linear phase.
The AD7762 employs three FIR filters in series. By using
different combinations of decimation ratios and filter selection
and bypassing, data can be obtained from the AD7762 at a large
range of data rates. The first filter receives data from the
modulator at ICLK MHz where it is decimated by four to
output data at ICLK/4 MHz. This partially filtered data can also
be output at this stage. The second filter allows the decimation
rate to be chosen from 4× to 32×. The third filter has a fixed
decimation rate of 2×, is user programmable, and has a default
configuration. It is described in detail in the Programmable FIR
Filter section. This filter can be bypassed.
Table 6 lists some characteristics of the default filter. The group
delay of the filter is defined to be the delay to the center of the
impulse response and is equal to the computation + filter delays.
The delay until valid data is available (the DVALID status bit is
set) is equal to 2× the filter delay + the computation delay.
04975-037
QUANTIZATION NOISE
fICLK\2
BAND OF INTEREST
a.
fICLK\2
NOISE SHAPING
BAND OF INTEREST
b.
fICLK\2
BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY
c.
Figure 22. Σ-Δ ADC
Table 6. Configuration with Default Filter
ICLK
Frequency
Filter 1
Filter 2
Filter 3
Data State
Computation
Delay
Filter Delay
Pass-Band
Bandwidth
Output Data
Rate (ODR)
20 MHz
4×
2×
Fully filtered
1.775 s
44.4 s
250 kHz
625 kHz
20 MHz
4×
8×
Bypassed
Partially filtered
2.6 s
10.8 s
140.625 kHz
625 kHz
20 MHz
4×
8×
2×
Fully filtered
2.25 s
87.6 s
125 kHz
312.5 kHz
20 MHz
4×
16×
Bypassed
Partially filtered
4.175 s
20.4 s
70.3125 kHz
312.5 kHz
20 MHz
4×
16×
2×
Fully filtered
3.1 s
174 s
62.5 kHz
156.25 kHz
20 MHz
4×
32×
Bypassed
Partially filtered
7.325 s
39.6 s
35.156 kHz
156.25 kHz
20 MHz
4×
32×
2×
Fully filtered
4.65 s
346.8 s
31.25 kHz
78.125 kHz
12.288 MHz
4×
8×
2×
Fully filtered
3.66 s
142.6 s
76.8 kHz
192 kHz
12.288 MHz
4×
16×
2×
Fully filtered
5.05 s
283.2 s
38.4 kHz
96 kHz
12.288 MHz
4×
32×
Bypassed
Partially filtered
11.92 s
64.45 s
21.6 kHz
96 kHz
12.288 MHz
4×
32×
2×
Fully filtered
7.57 s
564.5 s
19.2 kHz
48 kHz
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