參數(shù)資料
型號： EVAL-AD7762EDZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/29頁
文件大?。?/td> 0K
描述： BOARD EVAL CONTROL AD7762
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： ±3.25 Vpp
在以下條件下的電源（標準）： 958mW @ 625kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7762
已供物品： 板，CD
Data Sheet
AD7762
Rev. A | Page 15 of 28
CLOCKING THE AD7762
The AD7762 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7762. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
ICLK = MCLK (CDIV = 1)
ICLK = MCLK/2 (CDIV = 0)
These options are selected from the control register (see the
AD7762 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in Table 6, output data rates
of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
The MCLK jitter requirements depend on a number of factors
and are given by
20
)
dB
(
)
(
10
2
SNR
IN
rms
j
f
OSR
t
×
r
×
=
where:
OSR = Over-sampling ratio =
ODR
fICLK
fIN = Maximum input frequency
SNR(dB) = Target SNR
EXAMPLE 1
This example can be taken from Table 6, where:
ODR = 625 kHz
fICLK = 20 MHz
fIN (max) = 250 kHz
SNR = 108 dB
ps
6
.
3
10
250
2
32
6
3
)
(
=
×
r
×
=
rms
j
t
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
EXAMPLE 2
Take a second example from Table 6, where:
ODR = 48 kHz
fICLK = 12.288 MHz
fIN (max) = 19.2 kHz
SNR = 120 dB
ps
133
10
2
.
19
2
256
6
3
)
(
=
×
r
×
=
rms
j
t
The input amplitude also has an effect on these jitter figures.
If, for example, the input level was 3 dB below full scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.53 ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 23 and Figure 24 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
1
–1.0
04975-038
0.5
0
–0.5
Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
1
–1.0
04975-039
0.5
0
–0.5
Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with
Amplitude of 1 V p-p
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