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參數(shù)資料
| 型號： | EVAL-AD7781EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7781 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 470 |
| 數(shù)據(jù)接口： | SPI? |
| 輸入范圍： | ±5 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7781 |
| 已供物品： | 板 |
AD7781
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
0120
100
80
60
40
20
F
IL
T
E
R
GA
IN
(
d
B
)
INPUT SIGNAL FREQUENCY (Hz)
–120
0
–20
–40
–60
–80
–100
The AD7781 is a low power ADC that incorporates a precision,
20-bit, Σ-Δ modulator; a PGA; and an on-chip digital filter
intended for measuring wide dynamic range, low frequency
signals. The part provides a complete front-end solution for
bridge sensor applications such as weigh scales and pressure
sensors.
The device has an internal clock and one buffered differential
input. It offers a choice of two update rates (10 Hz or 16.7 Hz)
and two gain settings (1 or 128). These functions are controlled
using dedicated pins, which makes the interface easy to configure.
A 2-wire interface simplifies data retrieval from the AD7781.
FILTER, DATA RATE, AND SETTLING TIME
08
16
2-
0
20
The AD7781 has two filter options. When the FILTER pin is
low, the 16.7 Hz filter is selected; when the FILTER pin is high,
the 10 Hz filter is selected. When the polarity of the FILTER pin
is changed, the AD7781 modulator and filter are reset immedi-
ately. DOUT/RDY is set high, and the ADC begins conversions
using the selected filter response. The first conversion requires
the total settling time of the filter. Subsequent conversions
occur at the selected update rate. The settling time of the 10 Hz
filter is 300 ms (three conversion cycles), and the settling time
of the 16.7 Hz filter is 120 ms (two conversion cycles).
When a step change occurs on the analog input, the AD7781
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period, the
settling time of the AD7781 must be allowed to generate a valid
conversion. If the step change occurs asynchronous to the end
of a conversion, an extra conversion must be allowed to generate
a valid conversion. The data register is updated with all the con-
versions, but, for an accurate result, the user must allow for the
required time.
The 10 Hz filter provides more than 45 dB of rejection in the
stop band. The only external filtering required on the analog
inputs is a simple R-C filter to provide rejection at multiples of
the master clock. A 1 kΩ resistor in series with each analog input,
a 0.01 μF capacitor from each input to GND, and a 0.1 μF
capacitor from AIN(+) to AIN() are recommended.
When the filter is changed, DOUT/RDY goes high and remains
high until the appropriate settling time for that filter elapses
(see
). Therefore, the user should complete any read
operations before changing the filter. Otherwise, 1s are read
back from the AD7781 because the DOUT/
RDY pin is set high
following the filter change.
Figure 20. Filter Profile with Update Rate = 16.7 Hz (FILTER = 0)
0
120
100
80
60
40
20
F
IL
T
E
R
GA
IN
(
d
B
)
INPUT SIGNAL FREQUENCY (Hz)
–120
0
–20
–40
–60
–80
–100
08
16
2-
0
21
Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1)
The AD7781 has two gain options: gain = 1 and gain = 128.
When the GAIN pin is low, the gain is set to 128; when the
GAIN pin is high, the gain is set to 1. The acceptable analog
input range is ±VREF/gain. Thus, with VREF = 5 V, the input range
is ±5 V when GAIN is high and ±39 mV when GAIN is low.
When the polarity of the GAIN pin is changed, the AD7781 modu-
lator and filter are reset immediately. DOUT/RDY is set high, and
the ADC begins conversions. DOUT/RDY remains high until
the appropriate settling time for the filter elapses (see
).
Therefore, the user should complete any read operations before
changing the gain. Otherwise, 1s are read back from the AD7781
because the DOUT/
RDY pin is set high following the gain change.
The total settling time of the selected filter is required to generate
the first conversion after the gain change; subsequent conversions
occur at the selected update rate.
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