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參數(shù)資料
| 型號(hào)： | EVAL-AD7781EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7781 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 470 |
| 數(shù)據(jù)接口： | SPI? |
| 輸入范圍： | ±5 V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7781 |
| 已供物品： | 板 |
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AD7781
Rev. 0 | Page 13 of 16
DIGITAL INTERFACE
When a conversion is complete, the serial interface is reset, and
the new conversion is placed in the data register. Therefore, the
user must ensure that the complete word is read before the next
conversion is complete.
The serial interface of the AD7781 consists of two signals: SCLK
and DOUT/RDY. SCLK is the serial clock input for the device,
and data transfers occur with respect to the SCLK signal. The
DOUT/RDY pin is dual purpose: it functions as a data ready
pin and as a data output pin. DOUT/RDY goes low when a new
data-word is available in the output register. A 32-bit word is
placed on the DOUT/RDY pin when sufficient SCLK pulses are
applied. This word consists of a 20-bit conversion result followed
by four 0s to generate a 24-bit word. Following this, status bits
are output.
shows the status bits, and
describes
the status bits and their functions.
When PDRST is low, the DOUT/RDY pin is tristated. When
PDRST is taken high, the internal clock requires approximately
1 ms to power up. Following power-up, the ADC continuously
converts. The first conversion requires the total settling time
(see
). DOUT/
RDY goes high when PDRST is taken
high and returns low only when a conversion is available. The
ADC then converts continuously, and subsequent conversions
are available at the selected update rate.
shows the
timing for a read operation from the AD7781.
08
16
2-
02
2
FILTER
ERR
RDY
ID1
ID0
GAIN
PAT1
PAT0
When the filter response is changed (using the FILTER pin) or
the gain is changed (using the GAIN pin), the modulator and
filter are reset immediately (see Figure 5). DOUT/RDY is set
high. The ADC then begins conversions using the selected filter
response/gain setting. DOUT/RDY remains high until the appro-
priate settling time for that filter has elapsed. Therefore, the user
should complete any read operations before changing the gain or
update rate. Otherwise, 1s are read back from the AD7781 because
the DOUT/RDY pin is set high following the gain/filter change.
Figure 22. Status Bits
DOUT/RDY is reset high when the conversion has been read.
If the conversion is not read, DOUT/RDY goes high prior to the
data register update to indicate when not to read from the device.
This ensures that a read operation is not attempted while the reg-
ister is being updated. Each conversion can be read only once. The
data register is updated for every conversion.
Table 9. Status Bit Functions
Bit Name
Description
RDY
Ready bit.
0: a conversion is available.
FILTER
Filter bit.
1: 10 Hz filter is selected.
0: 16.7 Hz filter is selected.
ERR
Error bit.
1: an error occurred during conversion. (An error occurs when the analog input is out of range.)
ID1, ID0
ID bits.
ID1
ID0
Function
0
Indicates the ID number for the AD7781.
GAIN
Gain bit.
1: gain = 1.
0: gain = 128.
PAT1, PAT0
Status pattern bits. When the user reads data from the AD7781, a pattern check can be performed.
PAT1
PAT0
Function
0
1
Indicates that the serial transfer from the ADC was performed correctly (default).
0
Indicates that the serial transfer from the ADC was not performed correctly.
1
x
Indicates that the serial transfer from the ADC was not performed correctly.
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