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參數(shù)資料
| 型號： | EVAL-AD7843EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7843 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.25 V |
| 在以下條件下的電源（標準）： | 1.4mW @ 125kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7843 |
| 已供物品： | 板 |
| 相關產品： | AD7843ARUZ-ND - IC ADC 12BIT TOUCHSCREEN 16TSSOP AD7843ARUZ-REEL7-ND - IC ADC 12BIT TOUCHSCREEN 16TSSOP AD7843ARQZ-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP AD7843ARQZ-REEL7-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP AD7843ARQZ-REEL-ND - IC ADC 12BIT TOUCHSCREEN 16-QSOP |
AD7843
Rev. B | Page 3 of 20
SPECIFICATIONS
VCC = 2.7 V to 3.6 V, VREF = 2.5 V, fSCLK = 2 MHz, TA = 40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
AD7843A1
Unit
Test Conditions/Comments
DC ACCURACY
Resolution
12
Bits
No Missing Codes
11
Bits min
Integral Nonlinearity2
±2
LSB max
Offset Error2
±6
LSB max
VCC = 2.7 V
Offset Error Match3
1
LSB max
0.1
LSB typ
Gain Error2
±4
LSB max
Gain Error Match3
1
LSB max
0.1
LSB typ
Power Supply Rejection
70
dB typ
SWITCH DRIVERS
On-Resistance2
Y+, X+
5
typ
Y, X
6
typ
ANALOG INPUT
Input Voltage Ranges
0 to VREF
V
DC Leakage Current
±0.1
A typ
Input Capacitance
37
pF typ
REFERENCE INPUT
VREF Input Voltage Range
1.0/+VCC
V min/max
DC Leakage Current
±1
A max
VREF Input Impedance
5
G typ
CS = GND or +VCC
20
A max
8 A typ
1
A typ
fSAMPLE = 12.5 kHz
1
A max
CS = +VCC; 0.001 A typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.4
V max
Input Current, IIN
±1
A max
Typically 10 nA, VIN = 0 V or +VCC
Input Capacitance, CIN4
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VCC 0.2
V min
ISOURCE = 250 A; VCC = 2.2 V to 5.25 V
Output Low Voltage, VOL
0.4
V max
ISINK = 250 A
PENIRQ Output Low Voltage, VOL
0.4
V max
ISINK = 250 A; 100 kW pull-up
Floating-State Leakage Current
±10
A max
Floating-State Output Capacitance4
10
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
12
DCLK Cycles max
Track-and-Hold Acquisition Time
3
DCLK Cycles min
Throughput Rate
125
kSPS max
Footnotes on next page.
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