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參數(shù)資料
| 型號： | EVAL-AD7942SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7942 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7942 |
| 已供物品： | 板 |
AD7942
Rev. B | Page 14 of
24
AD7942
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE (NOTE 5)
100nF
5V
10F
(NOTE 2)
1.8V TO VDD
REF
0V TO VREF
33
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
NOTE 1: SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
NOTE 2: CREF IS USUALLY A 10F CERAMIC CAPACITOR (X5R).
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
04
65
7-
02
2
Figure 22. Typical Application Diagram
Transfer Functions
The ideal transfer characteristic for the AD7942 is shown in
000...000
000...001
000...010
111...101
111...110
111...111
ADC
CO
DE
(
S
T
RAI
G
HT
BI
N
A
R
Y)
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
04
65
7-
02
3
Figure 23. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FSR – 1 LSB
4.999695 V
Midscale + 1 LSB
2.500305 V
0x2001
Midscale
2.5 V
0x2000
Midscale – 1 LSB
2.499695 V
0x1FFF
–FSR + 1 LSB
305.2 μV
0x0001
–FSR
0 V
1 This is also the code for an overranged analog input (VIN+ – VIN > VREF – VGND).
2 This is also the code for an underranged analog input (VIN+ – VIN < VGND).
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended connection
diagram for the AD7942 when multiple supplies are available.
Analog Input
Figure 24 shows an equivalent circuit of the input structure of
the AD7942.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to become forward-
biased and to start conducting current. However, these diodes
can handle a forward-biased current of 130 mA maximum. For
instance, these conditions could eventually occur when the
input buffer (U1) supplies are different from VDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
CIN
RIN
D1
D2
CPIN
IN+
OR IN–
GND
VDD
04
65
7-
02
4
Figure 24. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the diffe-
rential signal between IN+ and IN. By using this differential
input, small signals common to both inputs are rejected, as
shown in Figure 25, which represents the typical CMRR over
frequency. For instance, by using IN to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated.
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