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參數(shù)資料
| 型號： | EVAL-AD7942SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7942 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7942 |
| 已供物品： | 板 |
AD7942
Rev. B | Page 17 of
24
CS Mode 3-Wire Without Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 30 and the corresponding timing
diagram is shown in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues to completion irres-
pective of the state of CNV. For instance, it is useful to bring
CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the acqui-
sition phase and powers down. When CNV goes low, the MSB
is output onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
14th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7942
04
65
7
-03
0
Figure 30. CS Mode 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDO
D13
D12
D11
D1
D0
tDIS
SCK
12
3
12
13
14
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
04
65
7-
0
31
Figure 31. CS Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)
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