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| 型號： | EVAL-AD7949EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7949 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 10.8mW @ 250kSPS，5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7949 |
| 已供物品： | 板 |
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Data Sheet
AD7949
Rev. D | Page 23 of 32
READING/WRITING SPANNING CONVERSION, ANY
SPEED HOST
When reading/writing spanning conversion, the data access starts
at the current acquisition (n) and spans into the conversion (n).
Conversion results are for the previous (n 1) conversion, and
writing the CFG register is for the next (n + 1) acquisition and
conversion.
Similar to reading/writing during conversion, reading/writing
should only occur up to tDATA. For the maximum throughput,
the only time restriction is that reading/writing take place
during the tACQ + tDATA time.
For slow throughputs, the time restriction is dictated by the
user’s required throughput, and the host is free to run at any
speed. Similar to reading/writing during acquisition, for slow
hosts, the data access must take place during the acquisition
phase with additional time into the conversion.
Note that data access spanning conversion requires the CNV to
be driven high to initiate a new conversion, and data access is
not allowed when CNV is high. Thus, the host must perform
two bursts of data access when using this method.
CONFIGURATION REGISTER, CFG
The AD7949 uses a 14-bit configuration register (CFG[13:0]),
as detailed in Table 9, to configure the inputs, the channel to be
converted, the one-pole filter bandwidth, the reference, and the
channel sequencer. The CFG register is latched (MSB first) on
DIN with 14 SCK rising edges. The CFG update is edge depen-
dent, allowing for asynchronous or synchronous hosts.
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