- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄17049 > EVAL-AD7949EDZ (Analog Devices Inc)BOARD EVAL AD7949 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-AD7949EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/32頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7949 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 10.8mW @ 250kSPS，5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7949 |
| 已供物品： | 板 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
AD7949
Data Sheet
Rev. D | Page 26 of 32
GENERAL TIMING WITH A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). As detailed previously, the data access should occur up
to safe data reading/writing time, tDATA. If the full CFG word is
not written to prior to EOC, it is discarded and the current
configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 15 SCK falling edges to return SDO to
high impedance because the last bit on SDO remains active.
Unlike the case detailed in the General Timing Without a Busy
Indicator section, if the conversion result is not read out fully
prior to EOC, the last bit clocked out remains. If this bit is low,
the busy signal indicator cannot be generated because the busy
generation requires either a high impedance or a remaining bit
high-to-low transition. Because most SPI hosts are usually
limited to 8-bit or 16-bit bursts, this should not be an issue.
Additional clocks are not a concern because SDO remains high
impedance after the 15th falling edge.
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2nd EOC; thus, two dummy conversions are
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n 1).
ACQUISITION
(n – 1) UNDEFINED
ACQUISITION
(n)
ACQUISITION
(n + 1)
ACQUISITION
(n + 2)
PHASE
POWER
UP
EOC
START OF CONVERSION
(SOC)
EOC
CONVERSION
(n)
CONVERSION
(n + 1)
CONVERSION
(n – 2) UNDEFINED
tCONV
tCYC
tDATA
CNV
DIN
RDC
RAC
RSC
SDO
NOTES
1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.
2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
DATA (n)
DATA (n – 2)
XXX
DATA (n – 2)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
DIN
SDO
DATA (n + 1)
DATA (n)
DATA (n + 1)
DIN
CFG (n)
CFG (n + 2)
CFG (n + 1)
CFG (n + 3)
SDO
SCK
1
SCK
1n
n + 1
15
1
n
n + 1
15
1
n
n + 1
15
SCK
1
XXX
NOTE 1
NOTE 2
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
CONVERSION
(n – 1) UNDEFINED
07
35
1-
03
7
DATA (n – 1)
XXX
DATA (n – 2)
XXX
DATA (n – 3)
XXX
DATA (n – 2)
XXX
DATA (n – 1)
XXX
Figure 37. General Interface Timing for the AD7949 With a Busy Indicator
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STD01W-H | WIRE & CABLE MARKERS |
| EVAL-AD7764EDZ | BOARD EVAL AD7764 |
| STD01W-U | WIRE & CABLE MARKERS |
| DK-DEV-1AGX60N | KIT DEV ARRIA GX 1AGX60N |
| GBM25DRSS | CONN EDGECARD 50POS DIP .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7951EDZ | 功能描述:BOARD EVAL FOR AD7951 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7960FMCZ | 制造商:Analog Devices 功能描述:AD7960 18BIT PULSAR DIFF ADC 制造商:Analog Devices 功能描述:EVAL BOARD, AD7960 ADC, Silicon Manufacturer:Analog Devices, Silicon Core Number:AD7960, Kit Application Type:Data Converter, Application Sub Type:ADC, Kit Contents:Eval Board AD7960,, Features:(Not Applicable) |
| EVAL-AD7961FMCZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL BOARD FOR AD7961 制造商:Analog Devices 功能描述:AD7961 16BIT PULSAR DIFF ADC 制造商:Analog Devices 功能描述:EVAL BOARD, AD7961 ADC, Silicon Manufacturer:Analog Devices, Silicon Core Number:AD7961, Kit Application Type:Data Converter, Application Sub Type:ADC, Kit Contents:Eval Board AD7961, Features:(Not Applicable) |
| EVAL-AD7980CBZ | 功能描述:BOARD EVAL CONTROL AD7980 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7980SDZ | 功能描述:BOARD EVAL FOR AD7980 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。