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參數(shù)資料
| 型號(hào)： | EVAL-AD7949EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 17/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7949 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 10.8mW @ 250kSPS，5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7949 |
| 已供物品： | 板 |
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AD7949
Data Sheet
Rev. D | Page 24 of 32
The register can be written to during conversion, during acquisi-
tion, or spanning acquisition/conversion, and is updated at the end
of conversion, tCONV (maximum). There is always a one deep
delay when writing the CFG register. Note that, at power-up, the
CFG register is undefined and two dummy conversions are
required to update the register. To preload the CFG register with a
factory setting, hold DIN high for two conversions. Thus
CFG[13:0] = 0x3FFF. This sets the AD7949 for the following:
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for a one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
Enables the internal sequencer
No readback of the CFG register
Table 9 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INx
BW
REF
SEQ
RB
Table 9. Configuration Register Description
Bit(s)
Name
Description
[13]
CFG
Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register.
[12:10]
INCC
Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer
to the
Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
X1
Bipolar differential pairs; INx referenced to VREF/2 ± 0.1 V.
0
1
0
Bipolar; INx referenced to COM = VREF/2 ± 0.1 V.
0
1
Temperature sensor.
1
0
X1
Unipolar differential pairs; INx referenced to GND ± 0.1 V.
1
0
Unipolar, INx referenced to COM = GND ± 0.1 V.
1
Unipolar, INx referenced to GND.
[9:7]
INx
Input channel selection in binary fashion.
Bit 9
Bit 8
Bit 7
Channel
0
IN0
0
1
IN1
…
1
IN7
[6]
BW
Select bandwidth for low-pass filter. Refer to the
0 = of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to .
1 = full BW.
[5:3]
REF
Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the
Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
Internal reference, REF = 2.5 V output, temperature enabled.
0
1
Internal reference, REF = 4.096 V output, temperature enabled.
0
1
0
External reference, temperature enabled.
0
1
External reference, internal buffer, temperature enabled.
1
0
External reference, temperature disabled.
1
External reference, internal buffer, temperature disabled.
[2:1]
SEQ
Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the
Channel Sequencer section.
Bit 2
Bit 1
Function
0
Disable sequencer.
0
1
Update configuration during sequence.
1
0
Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.
1
Scan IN0 to IN[7:0] (set in CFG[9:7]).
[0]
RB
Read back the CFG register.
0 = read back current configuration at end of data.
1 = do not read back contents of configuration.
1
X = don’t care.
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