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參數(shù)資料
| 型號： | EVAL-AD9393-ABZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD AD9393 |
| 標準包裝： | 1 |
| 主要目的： | 視頻，開關(guān)，HDMI |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9393 |
| 已供物品： | 板 |
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AD9393
Rev. 0 | Page 24 of 40
BT656 GENERATION
0x27—Bit[4], BT656 EN
This bit enables the output to be BT656-compatible with the
defined start of active video (SAV) and the end of active video
(EAV) controls to be inserted. These require specification of the
number of active lines, active pixels per line, and delays to place
these markers. 0 = disable BT656 video mode. 1 = enable BT656
video mode. The power-up default setting is 0.
0x27—Bit[3], Force DE Generation
This bit allows the use of the internal DE generator in DVI
mode. 0 = internal DE generation disabled. 1 = force DE
generation via programmed registers. The power-up default
setting is 0.
0x27—Bits[2:0], Interlace Offset
These bits define the offset in HSYNCs from Field 0 to Field 1.
The power-up default setting is 000.
0x28—Bits[7:2], VSYNC Delay
These bits set the delay (in lines) from the leading edge of
VSYNC to active video. The power-up default setting is 24d.
0x28—Bits[1:0], HSYNC Delay MSB and 0x29—Bits[7:0],
HSYNC Delay LSB
These 10 bits set the delay (in pixels) from the HSYNC leading
edge to the start of active video. The power-up default setting is
0x104.
0x2A—Bits[3:0], Line Width MSB and 0x2B—Bits[7:0]
Line Width LSB
These 12 bits set the width of the active video line (in pixels).
The power-up default setting is 0x500.
0x2C—Bits[3:0], Screen Height MSB and 0x2D—Bits[7:0]
Screen Height LSB
These 12 bits set the height of the active screen (in lines). The
power-up default setting is 0x2D0.
0x2E—Bit[7], CTRL EN
When set, this bit allows CTRL[3:0] signals decoded from the
DVI to be output on the I2S data pins. 0 = I2S signals on I2S
lines. 1 = CTRL[3:0] output on I2S lines. The power-up default
setting is 0.
0x2E—Bits[6:5], I2S Output Mode
These bits select between four options for the I2S output: I2S,
right-justified, left-justified, or raw IEC60958 mode. The
power-up default setting is 00. See Table 13.
Table 13. I2S Output Select
I2S Output Mode
Result
00
I2S mode
01
Right-justified
10
Left-justified
11
Raw IEC60958 mode
0x2E—Bits[4:0], I2S Bit Width
These bits set the I2S bit width for right-justified mode. The
power-up default setting is 24 bits.
0x2F—Bit[6], TMDS Sync Detect
This read-only bit indicates the presence of a TMDS DE.
0 = no TMDS DE present. 1 = TMDS DE detected.
0x2F—Bit[5], TMDS Active
This read-only bit indicates the presence of a TMDS clock.
0 = no TMDS clock present. 1 = TMDS clock detected.
0x2F—Bit[4], AV Mute
This read-only bit indicates the presence of AV mute based on
general control packets. 0 = AV not muted. 1 = AV muted.
0x2F—Bit[3], HDCP Keys Read
This read-only bit reports if the HDCP keys were read
successfully. 0 = failure to read HDCP keys. 1 = HDCP
keys read.
0x2F—Bits[2:0], HDMI Quality
These read-only bits indicate a level of HDMI quality based
on the DE (display enable) edges. A larger number indicates
a higher quality.
0x30—Bit[6], HDMI Content Encrypted
This read-only bit is high when HDCP decryption is in use
(content is protected). The signal goes low when HDCP is
not being used. Use this bit to to allow copying of the content.
Sample the bit at regular intervals because it can change on a
frame-by-frame basis. 0 = HDCP not in use. 1 = HDCP
decryption in use.
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