參數(shù)資料
型號(hào)： EVAL-AD9393-ABZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/40頁
文件大?。?/td> 0K
描述： EVAL BOARD AD9393
標(biāo)準(zhǔn)包裝： 1
主要目的： 視頻，開關(guān)，HDMI
嵌入式： 否
已用 IC / 零件： AD9393
已供物品： 板
AD9393
Rev. 0 | Page 12 of 40
2-WIRE SERIAL REGISTER MAP
The AD9393 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 9. Control Register Map
Hex Address
Read/Write
Bits
Default
Value
Register Name
Description
0x00
Read
[7:0]
00000000
Chip revision
Chip revision ID. Revision is read [7:4] = major revision. [3:0]
= minor revision.
0x01
Read/write
[7:0]
01101001
PLL divider MSB
PLL feedback divider value MSB.
0x02
Read/write
[7:4]
1101xxxx
PLL divider LSB
PLL feedback divider value LSB.
0x03
Read/write
[7:6]
01xxxxxx
VCO range
VCO range.
[5:3]
xx001xxx
Charge pump
Charge pump current control for PLL.
[2]
xxxxx0xx
PLL enable
This bit enables a lower frequency to be used for audio
MCLK generation.
0x11
Read/write
[7:0]
00000000
Reserved
Must be set to 0x00 (default).
0x12
Read/write
[7]
1xxxxxxx
Input HSYNC polarity
0 = active low.
1 = active high.
[6]
x0xxxxxx
HSYNC polarity override
0 = auto HSYNC polarity.
1 = manual HSYNC polarity.
[5]
xx1xxxxx
Input VSYNC polarity
0 = active low.
1 = active high.
[4]
xxx0xxxx
VSYNC polarity override
0 = auto VSYNC polarity.
1 = manual VSYNC polarity.
0x17
Read
[3:0]
xxxx0000
HSYNCs per VSYNC MSB
MSB of HSYNCs per VSYNC.
0x18
Read
[7:0]
00000000
HSYNCs per VSYNC LSB
HSYNCs per VSYNC count.
0x22
Read/write
[7:0]
4
VSYNC duration
VSYNC duration.
0x23
Read/write
[7:0]
32
HSYNC duration
HSYNC duration. Sets the duration of the output HSYNC in
pixel clocks.
0x24
Read/write
[7]
1xxxxxxx
HSYNC output polarity
Output HSYNC polarity.
0 = active low output.
1 = active high output.
[6]
x1xxxxxx
VSYNC output polarity
Output VSYNC polarity.
0 = active low output.
1 = active high output.
[5]
xx1xxxxx
DE output polarity
Output DE polarity.
0 = negative output.
1 = positive output.
[4]
xxx1xxxx
Field output polarity
Output field polarity.
0 = active low output.
1 = active high output.
[0]
xxxxxxx0
Output CLK invert
0 = noninverted clock output.
1 = inverted clock output.
0x25
Read/write
[7:6]
01xxxxxx
Output CLK select
Selects which clock to use on output ball. 1× CLK is divided
down from TMDS clock input when pixel repetition is in use.
00 = × CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1× CLK.
[5:4]
xx11xxxx
Output drive strength
Sets the drive strength of the outputs. 00 = lowest, 11 =
highest.
[3:2]
xxxx00xx
Output mode
Selects the data output mapping.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on D[7:0].
10 = DDR 4:4:4 + DDR 4:2:2 on D[7:0].
11 = 12-bit 4:2:2.
[1]
xxxxxx1x
Primary output enable
Enables primary output.
[0]
xxxxxxx0
Secondary output enable
Enables secondary output (DDR 4:2:2 in Output Mode 1
and Output Mode 2).
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