參數(shù)資料
型號(hào)： EVAL-ADF4350EB1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/32頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD 1 FOR ADF4350
設(shè)計(jì)資源： Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144)
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4350
主要屬性： 帶 VCO 的單路分?jǐn)?shù)-N 和整數(shù)-N PLL
次要屬性： USB 接口
已供物品： 板，纜線，CD
其它名稱： Q4437453
Q4841122
Q5095480
Q5242312
Q5416250
Wideband Synthesizer with Integrated VCO
ADF4350
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency range: 137.5 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16 output
Typical rms jitter: <0.4 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
GENERAL DESCRIPTION
The ADF4350 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external loop filter and external reference
frequency.
The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CPOUT
LD
SW
VCOM
TEMP
REFIN
CLK
DATA
LE
AVDD
SDVDD
DVDD
VP
AGND
CE
DGND
CPGND
SDGND
AGNDVCO
RSET
VVCO
VTUNE
VREF
RFOUTA+
RFOUTA–
RFOUTB+
RFOUTB–
VCO
CORE
PHASE
COMPARATOR
FLO SWITCH
CHARGE
PUMP
OUTPUT
STAGE
OUTPUT
STAGE
PDBRF
MULTIPLEXER
M
U
LT
IP
LE
X
E
R
10-BIT R
COUNTER
÷2
DIVIDER
×2
DOUBLER
FUNCTION
LATCH
DATA REGISTER
INTEGER
REG
N COUNTER
FRACTION
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
REG
MULTIPLEXER
LOCK
DETECT
÷1/2/4/8/16
ADF4350
07
32
5-
0
01
Figure 1.
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