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參數(shù)資料
型號(hào)： EVAL-ADF4350EB1Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/32頁(yè)
文件大小： 0K
描述： EVALUATION BOARD 1 FOR ADF4350
設(shè)計(jì)資源： Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144)
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4350
主要屬性： 帶 VCO 的單路分?jǐn)?shù)-N 和整數(shù)-N PLL
次要屬性： USB 接口
已供物品： 板，纜線，CD
其它名稱： Q4437453
Q4841122
Q5095480
Q5242312
Q5416250
ADF4350
Rev. A | Page 7 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
2
DATA
3
LE
4
CE
5
SW
6
7
24
VREF
23
VCOM
22
21
20
19
18
17
8
SD
V
DD
ADF4350
TOP VIEW
(Not to Scale)
9
AG
ND
10
AV
DD
11
RE
F
IN
12
DG
ND
13
DV
DD
14
15
16
32
31
30
29
28
SD
GN
D
27
26
25
PIN 1
INDICATOR
VP
CPOUT
CPGND
MU
X
O
U
T
RSET
RF
OU
T
A+
RF
OU
T
B+
RF
OU
T
B
RF
OU
T
A
V
VCO
VTUNE
AGNDVCO
TEMP
PD
B
RF
LD
A
GN
D
V
C
O
VVCO
073
25
-00
3
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
4
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device depending on the status of the power-down bits.
5
SW
Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.
6
VP
Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to
be placed as close as possible to this pin.
7
CPOUT
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is
connected to VTUNE to drive the internal VCO.
8
CPGND
Charge Pump Ground. This is the ground return pin for CPOUT.
9
AGND
Analog Ground. This is a ground return pin for AVDD.
10
AVDD
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are
to be placed as close as possible to this pin. AVDD must have the same value as DVDD.
11, 18, 21
AGNDVCO
VCO Analog Ground. These are the ground return pins for the VCO.
12
RFOUTA+
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
13
RFOUTA
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
14
RFOUTB+
Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
15
RFOUTB
Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
16, 17
VVCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to these pins. VVCO must have the same value as AVDD.
19
TEMP
Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as
possible to this pin.
20
VTUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
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