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| 型號(hào)： | EVAL-ADF4360-2EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 1/24頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-2 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-2 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 2GHz，200kHz PFD |
| 已供物品： | 板，線(xiàn)纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4360-2BCPZRL7-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-2BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-2BCPZ-ND - IC SYNTHESIZER/VCO 24-LFCSP |
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Integrated Synthesizer and VCO
Data Sheet
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency range: 1850 MHz to 2170 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-2 is a fully integrated integer-N synthesizer
and voltage-controlled oscillator (VCO). The ADF4360-2 is
designed for a center frequency of 2000 MHz. In addition, a
divide-by-2 option is available, whereby the user gets an RF
output of between 925 MHz and 1085 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
VVCO
REFIN
CLK
DATA
LE
AVDD
DVDD
CE
AGND
DGND
CPGND
RSET
VTUNE
CC
CN
RFOUTA
RFOUTB
VCO
CORE
PHASE
COMPARATOR
MUTE
DIVSEL = 2
DIVSEL = 1
N = (BP + A)
LOAD
CHARGE
PUMP
OUTPUT
STAGE
MULTIPLEXER
INTEGER
REGISTER
13-BIT B
COUNTER
14-BIT R
COUNTER
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
5-BIT A
COUNTER
PRESCALER
P/P+1
MULTIPLEXER
LOCK
DETECT
÷2
ADF4360-2
04436-001
Figure 1.
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