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參數(shù)資料
| 型號： | EVAL-ADF4360-2EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4360-2 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-2 |
| 主要屬性： | 帶 VCO 的單路整數(shù)-N PLL |
| 次要屬性： | 2GHz，200kHz PFD |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4360-2BCPZRL7-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-2BCPZRL-ND - IC SYNTHESIZER VCO 24LFCSP ADF4360-2BCPZ-ND - IC SYNTHESIZER/VCO 24-LFCSP |
Data Sheet
ADF4360-2
Rev. C | Page 11 of 24
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bit PC1 and Bit PC2 in the control latch. For VCO frequencies
above 2 GHz, only the 15 mA core current should be used, and
for frequencies below 2 GHz, only 20 mA core current should
be used.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 15. To
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch. Four
current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of 13 dBm, 11 dBm,
8 dBm, and 6 dBm, respectively, using a 50 resistor to VDD
and ac coupling into a 50 load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
VCO
RFOUTA
RFOUTB
BUFFER/
DIVIDE-BY-2
04436-015
Figure 15. Output Stage ADF4360-2
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