參數(shù)資料
型號(hào)： EVAL-ADUC7039QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7039
設(shè)計(jì)資源： ADuC7039QSPZ Gerber Files
EVAL-ADuC7039 Schematic & Brd Outline
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7039
所含物品： 板
ADuC7039
Data Sheet
Rev. D | Page 10 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
RESET
I
Reset Input Pin. Active low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When not in
use, this pin can be left unconnected. For added security and robustness, it is recommended that this
pin be strapped via a resistor to REG_DVDD.
2
TDO
O
JTAG Test Data Output. This data output pin is one of the standard 6-pin JTAG debug ports on the
part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an internal,
weak, pull-up resistor. This pin can be left unconnected when not in use.
3
TCK
I
JTAG Test Clock. This clock input pin is one of the standard 6-pin JTAG debug ports on the part. TCK
is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected when
not in use.
4
TMS
I
JTAG Test Mode Select. This mode select input pin is one of the standard 6-pin JTAG debug ports on
the part. TMS is an input pin only and has an internal, weak, pull-up resistor. This pin can be left
unconnected when not in use.
5
TDI
I
JTAG Test Data Input. This data input pin is one of the standard 6-pin JTAG debug ports on the part.
TDI is an input pin only and has an internal, weak, pull-up resistor. This pin can be left unconnected
when not in use.
6
NTRST
I
JTAG Test Reset. This reset input pin is one of the standard 6-pin JTAG debug ports on the part.
NTRST is an input pin only and has an internal, weak, pull-down resistor. This pin can be left uncon-
nected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN boot load mode.
7
RTCK
O
JTAG Return Test Clock. This output pin is used to adjust the JTAG clock speed to the highest possible
rate of the ADuC7039.
8
NC
No Connect. This pin is internally connected; therefore, do not externally connect this pin.
9
GND_SW
I
Switch to Internal Analog Ground Reference. This pin is the negative input for the external temperature
channel and external reference. If this input is not used, connect it directly to the AGND system ground.
10
VTEMP
I
External Pin for NTC/PTC Temperature Measurement.
11, 14, 15
AGND
S
Ground Reference for On-Chip Precision Analog Circuits.
12
IIN+
I
Positive Differential Input for Current Channel.
13
IIN
I
Negative Differential Input for Current Channel.
16, 17
REG_AVDD
S
Nominal 2.6 V analog Output from On-Chip Regulator. Pin 16 and Pin 17 must be connected together
to a capacitor to ground.
18, 19
REG_DVDD
S
Nominal 2.6 V digital Output from On-Chip Regulator. Pin 18 and Pin 19 must be connected together
to capacitors to ground.
20
DGND
S
Ground Reference for On-Chip Digital Circuits.
NOTES:
1. FOR DETAILS ON NC PINS, SEE THE PIN FUNCTION
DESCRIPTIONS TABLE.
2. EPAD IS INTERNALLY CONNECTED TO DGND.
1
GPIO_3/MOSI
2
GPIO_2/MISO
3
GPIO_1/SCLK
4
GPIO_0/SS
5
DGND
6
REG_DVDD
7
REG_DVDD
8REG_AVDD
24
23
22
21
20
19
18
17
RESET
TDO
TCK
TMS
TDI
NTRST
RTCK
NC
9
10
11
12
13
14
15
16
G
ND_S
W
VTE
M
P
AG
ND
IIN
+
IIN
–
AG
ND
AG
ND
RE
G
_
AV
DD
32
31
30
29
28
27
26
25
GP
IO_
5
VS
S
IO_
V
S
LIN
V
BAT
VD
D
NC
GP
IO_
4
/IR
Q1
TOP VIEW
(Not to Scale)
ADuC7039
08463
-00
3
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