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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 45 of 92
ADC Calibration
As shown in detail in the top level diagrams (Figure 11 and
Figure 12), the signal flow through all ADC channels can be
described in the following steps:
1. An input voltage is applied through an input buffer (and
PGA in the case of the I-ADC) to the Σ-Δ modulator.
2. The modulator output is applied to a programmable digital
decimation filter.
3. The filter output result is then averaged if chopping is used.
4. An offset value (ADCxOF) is subtracted from the result.
5. This result is scaled by a gain value (ADCxGN).
6. Finally, the result is formatted as twos complement/
unipolar, rounded to 16 bits, or clamped to ± full scale.
Each ADC channel (current, voltage, and temperature) has a
specific offset and gain correction or calibration coefficient
associated with it that are stored in MMR-based offset and
gain registers (ADCxOF and ADCxGN). The offset and gain
registers can be used to remove system level offset and gain
errors external to the part.
These registers are configured at power-on with a factory
programmed calibration value. These factory calibration
values vary from part to part reflecting the manufacturing
variability of internal ADC circuits. These registers can also
be overwritten by user code after a calibration.
On the current channel when a system calibration is initiated,
the ADC generates its calibration coefficient based on an
externally generated zero-scale voltage and full-scale voltage,
which are applied to the external ADC input for the duration
of the calibration cycle. The coefficients are written in the
ADC0DAT MMR of the ADC channels; they are not auto-
matically written in the ADC0OF or ADC0GN MMR. User
code must copy these values to their appropriate registers.
The duration of an offset calibration is a full ADC filter settling
time before returning the ADC to idle mode. When a calibra-
tion cycle is initiated, any ongoing ADC conversion is immediately
halted, the calibration is automatically carried out at an ADC
update rate programmed into ADCFLT, and the ADC is always
returned to idle after any calibration cycle. It is strongly recom-
mended that ADC calibration is initiated at as low an ADC
update rate as possible (high SF value in ADCFLT) to minimize
the impact of ADC noise during calibration.
On the voltage channel, a two-point calibration must be per-
formed as the minimum voltage specified on the input is 4 V.
The temperature channel is factory calibrated for the internal
temperature sensor.
Calibrating the Voltage Channel
To calibrate the offset and gain of the voltage channel a two-
point calibration method must be used. This method consists
of converting two known voltages (for example, 8 V and 16 V)
to determine lope and offset of the transfer function. The gain
coefficient can be divided by the calculated slope to improve
the gain error.
The offset error can be reduced by writing of the calculated
offset (in unipolar codes) into the ADC1OF MMR.
Calibrating the Current Channel
If the chop bit (ADCFLT[15]) is enabled, then internal ADC
offset errors are minimized and an offset calibration may not
be required. If chopping is disabled, however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
A gain calibration, particularly in the context of the I-ADC
(with internal PGA), may need to be carried out at all relevant
system gain ranges depending on system accuracy requirements.
If it is not possible to apply an external full-scale current on all
gain ranges, then it is possible to apply a lower current and scale
the result produced by the calibration. For example, apply a 50%
current and then divide the ADC0DAT value produced-by-two
and write this value back into ADC0GN. Note that there is a
lower limit to the input signal that can be applied for a system
calibration because ADC0GN is only a 16-bit register. The
input span (difference between the system zero-scale value
and system full-scale value) should be greater than 40% of the
nominal full-scale-input range, that is, >40% of VREF/gain.
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients. These can be copied by user code
directly into the relevant calibration registers, as appropriate,
based on the system configuration.
A factory, or end-of-line calibration, for the I-ADC is a two-
step procedure.
1. Apply the 0 A current. Configure the ADC in the required
PGA setting, and so on, and write to ADCMDE[2:0] to
perform a system zero-scale calibration. This writes a new
offset calibration value into ADC0DAT. User code must
store this value into ADC0OF or into Flash/EE memory.
2. Apply a full-scale current for the selected PGA setting.
Write to ADCMDE to perform a system full-scale cali-
bration. This writes a new gain calibration value into
ADC0DAT. This value must be copied by user software
to the ADC0GN MMR or into Flash/EE memory.
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