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| 型號： | EVAL-ADUC7039QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/92頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7039 |
| 設計資源： | ADuC7039QSPZ Gerber Files EVAL-ADuC7039 Schematic & Brd Outline |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關產品： | ADuC7039 |
| 所含物品： | 板 |
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Data Sheet
ADuC7039
Rev. D | Page 17 of 92
FLASH/EE MEMORY
The ADuC7039 incorporates Flash/EE memory technology
on chip to provide the user with nonvolatile, in-circuit
reprogrammable memory space.
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased, the erase being
performed in page blocks. Thus, flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. Incorporated within the
ADuC7039, Flash/EE memory technology allows the user to
update program code space in-circuit, without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
The Flash/EE memory is physically located at 0x80000. Upon a
hard reset, it logically maps to 0x00000000. The factory default
contents of all Flash/EE memory locations is 0xFFFF. Flash/EE
can be read in 8-/16-/32-bit segments, and written in segments
of 16 bits. The Flash/EE is rated for 10,000 endurance cycles.
This rating is based on the number of times that each individual
byte is cycled, that is, erased and programmed. Implementing a
redundancy scheme in the software ensures a greater than
10,000-cycle endurance.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
The entire Flash/EE is available to the user as code and non-
volatile data memory. There is no distinction between data and
program, because ARM code shares the same space. The real
width of the Flash/EE memory is 16 bits, meaning that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary for each instruction fetch. The ARM7TDMI-S
operates at a default 10.24 MHz clock frequency, but the Flash/EE
memory controller is operating at 20.48 MHz. This means that
the Flash/EE memory controller can transparently fetch the
second 16-bit half-word (part of the 32-bit ARM operation
code) within a single core clock period.
The page size of this Flash/EE memory is 512 bytes. Typically,
it takes the Flash/EE controller 20 ms to erase a page. To write a
16-bit word requires 50 μs.
It is possible to write to a single, 16-bit location at most twice
between erases; that is, it is possible to walk bytes, not bits. If
a location is written to more than twice, then it is possible to
corrupt the contents of the Flash/EE page.
The Flash/EE memory can be programmed in-circuit, using a
serial download mode via the LIN interface or the integrated
JTAG port.
Serial Downloading (In-Circuit Programming)
The ADuC7039 facilitates code download via the LIN pin.
The protocol is documented in the AN-946 Application
Note, Flash/EE Memory Programming via LIN (Protocol 6).
JTAG Access
The ADuC7039 features an on-chip JTAG debug port to
facilitate code download and debug.
FLASH/EE MMR INTERFACE
Access to, and control of, the Flash/EE memory on the ADuC7039
is managed by an on-chip memory controller. The controller
manages the Flash/EE memory as a single block of 64 kB.
Note that if executing from Flash/EE memory, the MCU core
is halted until the command is completed. User software must
ensure that the Flash/EE controller has completed any erase
or write cycle before the PLL is powered down. If the PLL is
powered down before an erase or write cycle is completed, the
Flash/EE page can be corrupted. User code, LIN, and JTAG
programming use the Flash/EE control interface, consisting
of the following MMRs:
FEESTA: read-only register, reflects the status of the
Flash/EE control interface.
FEEMOD: sets the operating mode of the Flash/EE control
interface.
FEECON: 8-bit command register. The commands are
interpreted as described in Table 10.
FEEDAT: 16-bit data register.
FEEADR: 16-bit address register.
FEESIG: holds the 24-bit code signature as a result of the
signature command being initiated.
FEEHID: protection MMR. Controls read and write
protection of the Flash/EE memory code space. If
previously configured via the FEEPRO register, FEEHID
can require a software key to enable access.
FEEPRO: a buffer of the FEEHID register that stores the
FEEHID value, thus, it automatically downloads to the
FEEHID registers on subsequent reset and power-on
events.
The following sections provide detailed descriptions of the bit
designations for each of the Flash/EE control MMRs.
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