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| 型號： | EVAL-ADUC842QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC842 |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關產(chǎn)品： | ADuC824 |
| 所含物品： | 評估板、電源、纜線、軟件和說明文檔 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 43 of 88
PWM Modes of Operation
Mode 0: PWM Disabled
The PWM is disabled allowing P2.6 and P2.7 to be used as
normal.
Mode 1: Single Variable Resolution PWM
In Mode 1, both the pulse length and the cycle time (period) are
programmable in user code, allowing the resolution of the
PWM to be variable.
PWM1H/L sets the period of the output waveform. Reducing
PWM1H/L reduces the resolution of the PWM output but
increases the maximum output rate of the PWM. For example,
setting PWM1H/L to 65536 gives a 16-bit PWM with a maxi-
mum output rate of 266 Hz (16.777 MHz/65536). Setting
PWM1H/L to 4096 gives a 12-bit PWM with a maximum
output rate of 4096 Hz (16.777 MHz/4096).
PWM0H/L sets the duty cycle of the PWM output waveform, as
shown in Figure 48.
P2.7
PWM COUNTER
PWM1H/L
0
PWM0H/L
03260-0-047
Figure 48. PWM in Mode 1
Mode 2: Twin 8-Bit PWM
In Mode 2, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are both programmable. The maximum
resolution of the PWM output is 8 bits.
PWM1L sets the period for both PWM outputs. Typically, this is
set to 255 (FFH) to give an 8-bit PWM, although it is possible to
reduce this as necessary. A value of 100 could be loaded here to
give a percentage PWM, i.e., the PWM is accurate to 1%.
The outputs of the PWM at P2.6 and P2.7 are shown in Figure 49.
As can be seen, the output of PWM0 (P2.6) goes low when the
PWM counter equals PWM0L. The output of PWM1 (P2.7)
goes high when the PWM counter equals PWM1H and goes
low again when the PWM counter equals PWM0H. Setting
PWM1H to 0 ensures that both PWM outputs start simultaneously.
P2.7
P2.6
PWM COUNTER
PWM1H
0
PWM1L
PWM0H
PWM0L
03260-0-048
Figure 49. PWM Mode 2
Mode 3: Twin 16-Bit PWM
In Mode 3, the PWM counter is fixed to count from 0 to 65536,
giving a fixed 16-bit PWM. Operating from the 16.777 MHz
core clock results in a PWM output rate of 256 Hz. The duty
cycle of the PWM outputs at P2.6 and P2.7 is independently
programmable.
As shown in Figure 50, while the PWM counter is less than
PWM0H/L, the output of PWM0 (P2.6) is high. Once the PWM
counter equals PWM0H/L, PWM0 (P2.6) goes low and remains
low until the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/L, the
output of PWM1 (P2.7) is high. Once the PWM counter equals
PWM1H/L, PWM1 (P2.7) goes low and remains low until the
PWM counter rolls over.
In this mode, both PWM outputs are synchronized, i.e., once
the PWM counter rolls over to 0, both PWM0 (P2.6) and
PWM1 go high.
P2.7
P2.6
PWM COUNTER
PWM1H/L
0
65536
PWM0H/L
03260-0-049
Figure 50. PWM Mode 3
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