參數(shù)資料
型號(hào)： EVAL-ADUC842QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 70/88頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC842
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC824
所含物品： 評(píng)估板、電源、纜線、軟件和說(shuō)明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 72 of 88
HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design
considerations that must be addressed when integrating the
ADuC841/ADuC842/ADuC843 into any hardware system.
Clock Oscillator
The clock source for the parts can be generated by the internal
PLL or by an external clock input. To use the internal PLL, con-
nect a 32.768 kHz parallel resonant crystal between XTAL1 and
XTAL2, and connect a capacitor from each pin to ground as
shown in Figure 75. The parts contain an internal capacitance of
18 pF on the XTAL1 and XTAL2 pins, which is sufficient for
most watch crystals. This crystal allows the PLL to lock correctly
to give an fVCO of 16.777216 MHz. If no crystal is present, the
PLL will free run, giving an fVCO of 16.7 MHz ±20%. In this mode,
the CD bits are limited to CD = 1, giving a max core clock of
8.38 MHz. This is useful if an external clock input is required.
The part powers up and the PLL will free run; the user then
writes to the CFG842 SFR in software to enable the external clock
input on P3.4. Note that double the required clock must be pro-
vided externally since the part runs at CD = 1. A better solution is
to use the ADuC841 with the external clock.
For the ADuC841, connect the crystal in the same manner; external
capacitors should be connected as per the crystal manufacturer’s
recommendations. A minimum capacitance of 20 pF is
recommended on XTAL1 and XTAL2. The ADuC841 will not
operate if no crystal is present.
An external clock may be connected as shown in Figure 76 and
Figure 77.
XTAL2
XTAL1
TO INTERNAL
TIMING CIRCUITS
ADuC841/ADuC842/ADuC843
03260-0-076
Figure 75. External Parallel Resonant Crystal Connections
XTAL2
XTAL1
TO INTERNAL
TIMING CIRCUITS
ADuC841
03260-0-075
EXTERNAL
CLOCK
SOURCE
Figure 76. Connecting an External Clock Source (ADuC841)
P3.4
TO INTERNAL
TIMING CIRCUITS
ADuC842/ADuC843
03260-0-077
EXTERNAL
CLOCK
SOURCE
Figure 77. Connecting an External Clock Source (ADuC842/ADuC843)
Whether using the internal PLL or an external clock source, the
parts’ specified operational clock speed range is 400 kHz to
16.777216 MHz, (20 MHz, ADuC841). The core itself is static,
and functions all the way down to dc. But at clock speeds slower
that 400 kHz, the ADC can no longer function correctly. There-
fore, to ensure specified operation, use a clock frequency of at
least 400 kHz and no more than 20 MHz.
External Memory Interface
In addition to its internal program and data memories, the parts
can access up to 16 MBytes of external data memory (SRAM).
Note that the parts cannot access external program memory.
Figure 78 shows a hardware configuration for accessing up to
64 kBytes of external RAM. This interface is standard to any
8051 compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC841/
ADuC842/
ADuC843
RD
P2
ALE
P0
WE
WR
03260-0-078
Figure 78. External Data Memory Interface (64 kBytes Address Space)
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