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參數(shù)資料
型號: EVAL-ADUC842QSZ
廠商: Analog Devices Inc
文件頁數(shù): 82/88頁
文件大小: 0K
描述: KIT DEV QUICK START ADUC842
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC824
所含物品: 評估板、電源、纜線、軟件和說明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 83 of 88
Parameter
SPI MASTER MODE TIMING (CPHA = 0)
Min
Typ
Max
Unit
tSL
SCLOCK Low Pulse Width1
476
ns
tSH
SCLOCK High Pulse Width1
476
ns
tDAV
Data Output Valid after SCLOCK Edge
50
ns
tDOSU
Data Output Setup before SCLOCK Edge
150
ns
tDSU
Data Input Setup Time before SCLOCK Edge
100
ns
tDHD
Data Input Hold Time after SCLOCK Edge
100
ns
tDF
Data Output Fall Time
10
25
ns
tDR
Data Output Rise Time
10
25
ns
tSR
SCLOCK Rise Time
10
25
ns
tSF
SCLOCK Fall Time
10
25
ns
1 Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK
(CPOL = 0)
t
DSU
SCLOCK
(CPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS 6–1
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
MSB IN
03260-0-093
Figure 92. SPI Master Mode Timing (CPHA = 0)
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