參數(shù)資料
型號: EVAL-ADV7623EB1Z
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADV7623
標準包裝: 1
系列: Xpressview™
主要目的: 視頻,視頻處理
已用 IC / 零件: ADV7623
已供物品:
ADV7623
Data Sheet
Rev. D | Page 4 of 16
SPECIFICATIONS
CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, TXAVDD = 1.8 V ± 5%,
TXPVDD = 1.8 V ± 5%, TXPLVDD = 1.8 V ± 5%, TMIN to TMAX = 0°C to 70°C.
DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL INPUTS
Input High Voltage (VIH)
2
V
Input Low Voltage (VIL)
0.8
V
Input Current (IIN)
RESET, EP_MISO, ALSB and CS pins
60
+60
A
Other digital inputs
10
+10
A
Input Capacitance (CIN)
10
pF
DIGITAL INPUTS (5 V TOLERANT)1
Input High Voltage (VIH)
2.6
V
Input Low Voltage (VIL)
0.8
V
Input Current (IIN)
82
+82
A
DIGITAL OUTPUTS
Output High Voltage (VOH)
2.4
V
Output Low Voltage (VOL)
0.4
V
High Impedance Leakage Current (ILEAK)
10
A
Output Capacitance (COUT)
20
pF
HDMI
TMDS Differential Pin Capacitance
0.3
pF
AC SPECIFICATIONS
Input Specifications
Intrapair (+ to ) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
0.4 tBIT
ps
Intrapair (+ to ) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
0.15 tBIT + 112
ps
Channel-to-Channel Differential Input Skew
0.2 tPIXEL + 1.78
ns
TMDS Input Clock Range
25
225
MHz
TMDS Input Clock Jitter Tolerance
0.5
0.25
tBIT
Output Specifications
TMDS Output Clock Frequency
20
225
MHz
TMDS Output Clock Duty Cycle
48
52
%
TMDS Output Differential Swing
900
1100
1200
mV
Differential Output Timing
Low-to-High Transition Time
75
175
ps
High-to-Low Transition Time
75
175
ps
1
The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL,
HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD, PWRDN, CEC, ARC+.
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