Y Version1 Parameter Min Typ Max Min Typ Max Unit Conditio" />
參數(shù)資料
型號: EVAL-CN0202-SDPZ
廠商: Analog Devices Inc
文件頁數(shù): 19/24頁
文件大小: 0K
描述: BOARD CFTL AD5662
設(shè)計資源: CN-0202 CFTL Eval/Design Support
標(biāo)準包裝: 1
系列: Circuits from the Lab™
主要目的: 參考設(shè)計,模擬輸出模塊
嵌入式:
已用 IC / 零件: AD5662,AD5750
已供物品:
其它名稱: EVAL-CN0202-SPDZ
EVAL-CN0202-SPDZ-ND
AD5662
Rev. A | Page 4 of 24
A Grade
B Grade
Y Version1
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
5.5
2.7
5.5
V
All digital inputs at 0 V or VDD
IDD (Normal Mode)
DAC active and excluding load current
VDD = 4.5 V to 5.5 V
150
250
150
250
μA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
140
225
140
225
μA
VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
0.48
1
0.48
1
μA
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
0.1
0.375
0.1
0.375
μA
VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD
90
%
ILOAD = 2 mA. VDD = 5 V
1 Temperature range is as follows: Y version: 40°C to +125°C, typical at +25°C.
2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024.
3 Guaranteed by design and characterization; not production tested.
4 Output unloaded.
5 Reference input range at ambient where ±1 LSB max DNL specification is achievable.
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