參數(shù)資料
型號: EVAL-CN0202-SDPZ
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: BOARD CFTL AD5662
設計資源: CN-0202 CFTL Eval/Design Support
標準包裝: 1
系列: Circuits from the Lab™
主要目的: 參考設計,模擬輸出模塊
嵌入式:
已用 IC / 零件: AD5662,AD5750
已供物品:
其它名稱: EVAL-CN0202-SPDZ
EVAL-CN0202-SPDZ-ND
AD5662
Rev. A | Page 17 of 24
AD5662 to 80C51/80L51 Interface
AD5662 to MICROWIRE Interface
Figure 39 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5662,
while RxD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
Figure 40 shows an interface between the AD5662 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5662
on the rising edge of the SK.
MICROWIRE*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04777-030
Figure 40. AD5662 to MICROWIRE Interface
80C51/80L51*
AD5662*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04777-029
Figure 39. AD5662 to 80C51/80L51 Interface
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